Document
SPN4812
N-Channel Enhancement Mode MOSFET
DESCRIPTION The SPN4812 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density , DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application , notebook computer power management and other battery powered circuits where high-side switching .
APPLICATIONS DC/DC Converter Load Switch Synchronous Buck Converter SMPS Secondary Side Synchronous Rectifier Power Tool Motor Control
FEATURES 100V/12A,RDS(ON)=12mΩ@VGS=10V 100V/10A,RDS(ON)=15mΩ@VGS=4.5V Super high density cell design for extremely low
RDS (ON) Exceptional on-resistance and maximum DC
current capability SOP–8 package design
PIN CONFIGURATION(SOP–8)
2020/03/27 Ver 2
PART MARKING
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SPN4812
N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8
Symbol S S S G D D D D
Description Source Source Source Gate Drain Drain Drain Drain
ORDERING INFORMATION
Part Number
Package
SPN4812S8RGB
SOP-8
※ SPN4812S8RGB : 13” Tape Reel ; Pb – Free ; Halogen – Free
ABSOULTE MAXIMUM RATINGS (TA=25℃ Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage Continuous Drain Current(TJ=150℃) Pulsed Drain Current
TA=25℃ TA=70℃
Avalanche Energy, Single Pulse (L=0.1mH , Tc=25℃)
Power Dissipation
TA=25℃ TA=70℃
Operating Junction Temperature
Storage Temperature Range Thermal Resistance-Junction to Case Thermal Resistance-Junction to Ambient (steady state)
Symbol VDSS VGSS
ID
IDM EAS
PD TJ TSTG RθJC RθJA
Part Marking SPN4812
Typical 100
±20 12 8 60
22 3.1 2.2 -55/150 -55/150 0.85 75
Unit V V A A mJ W ℃ ℃
℃/W
2020/03/27 Ver 2
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SPN4812
N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS (TA=25℃ Unless otherwise noted)
Parameter
Symbol
Conditions
Static Drain-Source Breakdown Voltage Gate Threshold Voltage Gate Leakage Current
Zero Gate Voltage Drain Current
Drain-Source On-Resistance Forward Transconductance Gate Resistance Diode Forward Voltage Dynamic Total Gate Charge Total Gate Charge Gate-Source Charge Gate-Drain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
V(BR)DSS VGS=0V,ID=250uA
VGS(th) VDS=VGS,ID=250uA
IGSS
IDSS
RDS(on) gfs RG
VDS=0V,VGS=±20V
VDS=100V,VGS=0V TJ=25℃ VDS=100V,VGS=0V TJ=100℃ VGS=10V,ID=12A VGS=4.5V,ID=10A
VDS=5V,ID=12A
VGS=0V,VDS=Open, f=1MHz
VSD IS=12A,VGS=0V
Qg(10V)
Qg(4.5V) VDS=50V,VGS=10V Qgs ID=14A
Qgd
Ciss
Coss
VDS=50V,VGS=0V f=1MHz
Crss
td(on)
tr td(off)
VDD=50V, ID=14A,VGS=10V RG=10Ω
tf
Min. Typ Max. Unit
100 V
1.4 1.9 2.4 ±100 nA
1 uA
100
9.5 11.5
12 15
mΩ
45
S
1.5
Ω
0.9 1.2 V
29
14 nC
5
5
2275
162
pF
7.9
8
3 nS
26
4
2020/03/27 Ver 2
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SPN4812
N-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2020/03/27 Ver 2
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SPN4812
N-Channel Enhancement Mode MOSFET
TYPICAL CHARACTE.