Document
SPN7002V
N-Channel Enhancement Mode MOSFET
DESCRIPTION The SPN7002V is the N-Channel enhancement mode field effect transistors are produced using high cell density DMOS technology. These products have been designed to minimize on-state resistance while provide rugged, reliable, and fast switching performance. They can be used in most applications requiring up to 300mA DC and can deliver pulsed currents up to 1.0A. These products are particularly suited for low voltage, low current applications such as small servo motor control, power MOSFET gate drivers, and other switching applications.
APPLICATIONS Drivers: Relays, Solenoids, Lamps, Hammers,
Display, Memories, Transistors, etc. High saturation current capability. Direct
Logic-Level Interface: TTL/CMOS Battery Operated Systems Solid-State Relays
FEATURES 60V/0.50A , RDS(ON)=4.0Ω@VGS=10V 60V/0.30A , RDS(ON)=5.0Ω@VGS=5V Super high density cell design for extremely low
RDS (ON) Exceptional on-resistance and maximum DC
current capability SOT-523 (SC-89) package design
PIN CONFIGURATION (SOT-523 / SC-89)
PART MARKING
2020/04/15 Ver 3
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SPN7002V
N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION Pin 1 2 3
Symbol G S D
Description Gate Source Drain
ORDERING INFORMATION
Part Number
Package
SPN7002VS52RGB
SOT-523
※ SPN7002VS52RGB : Tape Reel ; Pb – Free; Halogen – Free
Part Marking 2V
ABSOULTE MAXIMUM RATINGS (TA=25℃ Unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDSS
Gate –Source Voltage - Continuous
VGSS
Gate –Source Voltage - Non Repetitive ( tp < 50μs)
VGSS
Continuous Drain Current(TJ=150℃)
TA=25℃
ID
Pulsed Drain Current ()
IDM
Power Dissipation Operating Junction Temperature
TA=25℃
PD
TJ
Storage Temperature Range
TSTG
Thermal Resistance-Junction to Ambient
RθJA
() Pulse width limited by safe operating area
Typical 60 ±20 ±40 0.35 1.0 0.15
-55 ~ 150 -55 ~ 150
830
Unit V V V A A W ℃ ℃
℃/W
2020/04/15 Ver 3
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SPN7002V
N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS (TA=25℃ Unless otherwise noted)
Parameter
Symbol
Conditions
Static Drain-Source Breakdown Voltage Gate Threshold Voltage Gate Leakage Current
Zero Gate Voltage Drain Current
Drain-Source On-Resistance Source-drain Current Source-drain Current (pulsed) Forward Transconductance Diode Forward Voltage
V(BR)DSS VGS=0V,ID=250uA
VGS(th) VDS=VGS,ID=250uA
IGSS VDS=0V,VGS=±20V
VDS=48V,VGS=0V IDSS VDS=48V,VGS=0V
TJ=55℃
RDS(on)
VGS=10V,ID=0.50A VGS= 5V,ID=0.30A
ISD
ISDM (2)
Gfs(1) VDS = 10 V, ID = 0.5 A
VSD(1) VGS = 0 V, IS = 0.12A
Dynamic
Total Gate Charge Gate-Source Charge Gate-Drain Charge
Qg
Qgs
VDD=30V, ID=1A, VGS=5V
Qgd
Input Capacitance Output Capacitance Reverse Transfer Capacitance
Ciss
Coss
VDS=25V, f=1MHz, VGS=0
Crss
Turn-On Time Turn-Off Time
td(on) tr
td(off) tf
VDD=30V, ID=0.5A RG=4.7Ω ,VGS=4.5V
(1) Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %.
(2) Pulse width limited by safe operating area.
Min. Typ M.