Document
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 4 — 11 March 2020
Product data sheet
1. General description
The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
• Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• 8-bit serial input • 8-bit serial or parallel output • Storage register with 3-state outputs • Shift register with direct clear • 100 MHz (typical) shift out frequency • Complies with JEDEC standard no. 7A • Input levels:
• For 74HC595-Q100: CMOS level • For 74HCT595-Q100: TTL level • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) • Multiple package options • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
3. Applications
• Serial-to-parallel data conversion • Remote control holding register
Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC595D-Q100 74HCT595D-Q100
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC595PW-Q100 -40 °C to +125 °C 74HCT595PW-Q100
TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm
74HC595BQ-Q100 -40 °C to +125 °C 74HCT595BQ-Q100
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm
SOT763-1
5. Functional diagram
14 DS 11 SHCP 10 MR
12 STCP
8-STAGE SHIFT REGISTER 8-BIT STORAGE REGISTER
Q7S 9
13 OE
Fig. 1. Functional diagram
11 12
SHCP STCP
14 DS
Q7S 9 Q0 15 Q1 1 Q2 2
Q3 3
Q4 4
Q5 5 Q6 6
Q7 7
MR OE
10 13 mna552
Fig. 2. Logic symbol
3-STATE OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 1 2 3 4 5 6 7 mna554
13
EN3
12 C2
10 R
SRG8
11
C1/
14 1D
2D
3
15
1
2
3
4
5
6
7
9
mna553
Fig. 3. IEC logic symbol
74HC_HCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 11 March 2020
© Nexperia B.V. 2020. All rights reserved
2 / 20
Nexperia
DS SHCP
MR
STCP OE
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
STAGE 0
DQ FF0
CP R
STAGES 1 TO 6
D
Q
STAGE 7
DQ FF7
CP R
Q7S
DQ LATCH CP
DQ LATCH CP
Q0
Fig. 4. Logic diagram
6. Pinning information
Q1 Q2 Q3 Q4 Q5 Q6
mna555 Q7
6.1. Pinning
74HC595-Q100 74HCT595-Q100
Q1 1 Q2 2
16 VCC 15 Q0
Q3 3
14 DS
Q4 4
13 OE
Q5 5
12 STCP
Q6 6
11 SHCP
Q7 7
10 MR
GND 8
9 Q7S
aaa-003476
Fig. 5. Pin configuration for SOT109-1 (SO16)
74HC595-Q100 74HCT595-Q100
Q1 1 Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 GND 8
16 VCC 15 Q0 14 DS 13 OE 12 STCP 11 SHCP 10 MR 9 Q7S
aaa-003477
Fig. 6. Pin configuration for SOT403-1 (TSSOP16)
74HC_HCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 11 March 2020
© Nexperia B.V. 2020. All rights reserved
3 / 20
Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
terminal 1 index area
74HC595-Q100 74HCT595-Q100
1 Q1 16 VCC
Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7
GND(1)
15 Q0 14 DS 13 OE 12 STCP 11 SHCP 10 MR
GND 8 Q7S 9
aaa-003478
Transparent top view
(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Fig. 7. Pin configuration for SOT763-1 (DHVQFN16).