Flash Memory. AT49F1025 Datasheet

AT49F1025 Datasheet PDF, Equivalent


Part Number

AT49F1025

Description

1-Megabit 64K x 16 5-volt Only Flash Memory

Manufacture

ATMEL Corporation

Total Page 13 Pages
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Download AT49F1025 Datasheet PDF


AT49F1025 Datasheet
Features
Single Voltage Operation
– 5V Read
– 5V Reprogramming
Fast Read Access Time - 45 ns
Internal Program Control and Timer
8K word Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Word By Word Programming - 10 µs/Word Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Small 10 x 14 mm VSOP Package
Typical 10,000 Write Cycles
Description
The AT49F1024 and the AT49F1025 are 5-volt-only in-system Flash Memories. Their
1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 45
ns with power dissipation of just 275 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA. The
only difference between the AT49F1024 and the AT49F1025 is the pinout. The
AT49F1024 is pin compatable with the AT27C1024, and the AT49F1025 is pin com-
patable with the AT29C1024.
(continued)
Pin Configurations
Pin Name Function
A0 - A15
Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O15 Data Inputs/Outputs
NC No Connect
AT49F1025 VSOP Top View
Type 1
10 x 14 mm
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
10 x 14 mm
40 OE
39 I/O0
38 I/O1
37 I/O2
36 I/O3
35 I/O4
34 I/O5
33 I/O6
32 I/07
31 GND
30 I/O8
29 I/O9
28 I/O10
27 I/O11
26 I/O12
25 I/O13
24 I/O14
23 I/O15
22 NC
21 CE
AT49F1024 VSOP Top View
Type 1
10 x 14 mm
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
NC
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 GND
39 A8
38 A7
37 A6
36 A5
35 A4
34 A3
33 A2
32 A1
31 A0
30 OE
29 I/O0
28 I/O1
27 I/O2
26 I/O3
25 I/O4
24 I/O5
23 I/O6
22 I/O7
21 GND
PLCC Top View
I/O12
I/O11
I/O10
I/O9
I/O8
GND
NC
I/O7
I/O6
I/O5
I/O4
7
8
9
10
11
12
13
14
15
16
17
39 A13
38 A12
37 A11
36 A10
35 A9
34 GND
33 NC
32 A8
31 A7
30 A6
29 A5
1-Megabit
(64K x 16)
5-volt Only
Flash Memory
AT49F1024
AT49F1025
Rev. 0765D–09/98
1

AT49F1025 Datasheet
To allow for simple in-system reprogrammability, the
AT49F1024/1025 does not require high input voltages for
programming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49F1024/1025 is performed by
erasing a block of data (entire chip or main memory block)
and then programming on a word by word basis. The typi-
cal word programming time is a fast 10 µs. The end of a
program cycle can be optionally detected by the DATA poll-
ing feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in
excess of 10,000 cycles.
The optional 8K words boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being erased or reprogrammed.
Block Diagram
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(56K WORDS)
OPTIONAL BOOT
BLOCK (8K WORDS)
1FFFH
0000H
Device Operation
READ: The AT49F1024/1025 is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
CHIP ERASE: When the boot block programming lockout
feature is not enabled, the boot block and the main memory
block will erase together from the same chip erase com-
mand (See command definitions table). If the boot block
lockout function has been enabled, data in the boot section
will not be erased. However, data in the main memory sec-
tion will be erased. After a chip erase, the device will return
to the read mode.
MAIN MEMORY ERASE: As an alternative to the chip
erase, a main memory block erase can be performed which
will erase all bytes not located in the boot block region to an
FFH. Data located in the boot region will not be changed
during a main memory block erase. The Main Memory
Erase command is a six bus cycle operation. The address
(5555H) is latched on the falling edge of the sixth cycle
while the 30H data input is latched on the rising edge of
WE. The main memory erase starts after the rising edge of
WE of the sixth cycle. Please see Main Memory Erase
cycle waveforms. The Main Memory Erase operation is
internally controlled; it will automatically time to completion.
WORD PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
2 AT49F1024/1025


Features Datasheet pdf Features • Single Voltage Operation • • • • • • • • – 5 V Read – 5V Reprogramming Fast Read A ccess Time - 45 ns Internal Program Con trol and Timer 8K word Boot Block With Lockout Fast Erase Cycle Time - 10 seco nds Word By Word Programming - 10 µs/W ord Typical Hardware Data Protection DA TA Polling For End Of Program Detection Small 10 x 14 mm VSOP Package Typical 10,000 Write Cycles Description The AT 49F1024 and the AT49F1025 are 5-volt-on ly in-system Flash Memories. Their 1 me gabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atm el’s advanced nonvolatile CMOS techno logy, the devices offer access times to 45 ns with power dissipation of just 2 75 mW over the commercial temperature r ange. When the device is deselected, th e CMOS standby current is less than 100 µA. The only difference between the A T49F1024 and the AT49F1025 is the pinou t. The AT49F1024 is pin compatable with the AT27C1024, and the AT49F1025 is pin compatable with the AT29C1024. (continued) 1-Mega.
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