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PE64909 Dataheets PDF



Part Number PE64909
Manufacturers Peregrine Semiconductor
Logo Peregrine Semiconductor
Description UltraCMOS Digitally Tunable Capacitor
Datasheet PE64909 DatasheetPE64909 Datasheet (PDF)

Product Description PE64909 is a DuNE™ technology-enhanced Digitally Tunable Capacitor (DTC) based on Peregrine’s UltraCMOS® technology. This highly versatile product supports a wide variety of tuning circuit topologies with emphasis on impedance matching and aperture tuning applications. PE64909 offers high RF power handling and ruggedness while meeting challenging harmonic and linearity requirements enabled by Peregrine’s HaRP™ technology. The device is controlled through the widely supported .

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Product Description PE64909 is a DuNE™ technology-enhanced Digitally Tunable Capacitor (DTC) based on Peregrine’s UltraCMOS® technology. This highly versatile product supports a wide variety of tuning circuit topologies with emphasis on impedance matching and aperture tuning applications. PE64909 offers high RF power handling and ruggedness while meeting challenging harmonic and linearity requirements enabled by Peregrine’s HaRP™ technology. The device is controlled through the widely supported 3-wire (SPI compatible) interface. All decoding and biasing is integrated on-chip and no external bypassing or filtering components are required. DuNE™ devices feature ease of use while delivering superior RF performance in the form of tuning accuracy, monotonicity, tuning ratio, power handling, size, and quality factor. With built-in bias voltage generation and ESD protection, DTC products provide a monolithically integrated tuning solution for demanding RF applications. Product Specification PE64909 UltraCMOS® Digitally Tunable Capacitor (DTC) 100-3000 MHz Features  3-wire (SPI compatible) serial interface with built-in bias voltage generation and ESD protection  DuNE™ technology enhanced  4-bit 16-state Digitally Tunable Capacitor  Shunt configuration C = 0.6 pF to 2.35 pF (3.9:1 tuning ratio) in discrete 117 fF steps  High RF power handling (30 Vpk RF) and linearity  Wide power supply range (2.3 to 4.8V) and low current consumption (typ. 140 μA at 2.75V)  High ESD tolerance of 2kV HBM on all pins Applications include:  Tunable antennas  Tunable matching networks  Tunable filter networks  Phase shifters Figure 1. Functional Diagram Figure 2. Package Type 10-lead 2 x 2 x 0.55 mm QFN Document No. DOC-86359-1 │ www.psemi.com 71-0090-01 ©2017 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE64909 Product Specification Table 1. Electrical Specifications @ 25 °C, VDD = 2.75V (In shunt configuration, RF- connected to GND) Parameter Condition Min Typ Max Unit Operating frequency Minimum capacitance (Cmin) Maximum capacitance (Cmax) Tuning ratio State 0000, 100 MHz State 1111, 100 MHz Cmax/Cmin, 100 MHz 100 3000 MHz 0.54 0.60 0.66 pF 1.88 2.35 2.82 3.9:1 pF Step size 4 bits (16 states), 100 MHz Quality factor at Cmin1 698 to 960 MHz, with LS removed 1710 to 2170 MHz, with LS removed Quality factor at Cmax1 Self resonant frequency 698 to 960 MHz, with LS removed 1710 to 2170 MHz, with LS removed State 0000 State 1111 Harmonics2 IMD3 2fo, 3fo: 698 to 915 MHz; PIN = +34 dBm, 50Ω 2fo, 3fo: 1710 to 1910 MHz; PIN = +32 dBm, 50Ω Bands I,II,V/VIII, +20 dBm CW @ TX freq, -15 dBm CW @ 2TX-RX freq, 50Ω Third order intercept point Shunt configuration derived from IMD3 spec (IP3) IP3 = (2PTX + Pblock - IMD3) / 2 Switching time3,4 State change to 10/90% delta capacitance between any two states 0.117 pF 40 40 29 13 9.1 3.7 GHz -36 dBm -36 dBm -105 dBm 65 dBm 12 μs Start-up time3 Wake-up time3,4 Time from VDD within specification to all performances within specification State change from Standby mode to RF state to all performances within specification 70 μs 70 μs Notes: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit Q = XC/R = (X-XL)/R, where X = XL+XC , XL = 2*pi*f*L, XC = -1/(2*pi*f*C), which is equal to removing the effect of parasitic inductance LS 2. In Shunt between 50 Ω ports. Pulsed RF input with 4620 μS period, 50% duty cycle, measured per 3GPP TS 45.005 3. DC path to ground at RF– must be provided to achieve specified performance 4. State change activated on falling edge of SEN following data word ©2017 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11 Document No. DOC-86359-1 │ UltraCMOS® RFIC Solutions PE64909 Product Specification Figure 3. Pin Configuration (Top View) Table 2. Pin Descriptions Pin # Pin Name Description 1 RF- Negative RF port1 2 RF- Negative RF port1 3 GND Ground2 4 VDD Power supply pin 5 SCL Serial interface clock input 6 SEN Serial interface latch enable input 7 SDA Serial interface data input 8 RF+ Positive RF port1 9 RF+ Positive RF port1 10 GND Ground2 Pad GND Exposed pad: ground for proper operation2 Notes: 1. For optimal performance, recommend tying pins 1-2 and pins 8-9 together on PCB 2. For optimal performance, recommend tying pins 3, 10, and exposed ground pad together on PCB Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE64909 in the 10-lead 2x2 mm QFN package is MSL1. Table 3. Operating Ranges Parameter Symbol Min Typ Max Unit Supply voltage Supply current (VDD = 2.75V) Standby current (VDD = 2.75V) Digital input high Digital input low RF input power (50Ω)1 698 to 915 MHz 1710 to 1910 MHz VDD 2.30 2.75 4.80 V IDD 140 200 μA IDD 25 μA VIH 1.2 1.8 3.1 V VIL 0 0 0.57 V +34 dBm +32 dBm Peak operating RF voltage2 VP to VM VP to RFGND 3.


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