Document
Features
• Complies with Intel Low-Pin Count (LPC) Interface Specification Revision 1.1 – Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles
• Auto-detection of FWH and LPC Memory Cycles – Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets – Can Be Used as LPC Flash for Non-Intel Chipsets
• Flexible, Optimized Sectoring for BIOS Applications – 32-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 16-Kbyte Sector, Seven 64-Kbyte Sectors – Or Memory Array Can Be Divided Into Eight Uniform 64-Kbyte Sectors for Erasing
• Two Configurable Interfaces – FWH/LPC Interface for In-System Operation – Address/Address Multiplexed (A/A Mux) Interface for Programming during Manufacturing
• FWH/LPC Interface – Operates with the 33 MHz PCI Bus Clock – 5-signal Communication Interface Supporting Byte Reads and Writes – Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All Other Sectors – Five General-purpose Input (GPI) Pi.