S70KL1281

Not Recommended for New Designs (NRND) S27KL0641/S27KS0641 S70KL1281/S70KS1281 3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB), HyperRAM™ Self-Refresh DRAM 3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB), HyperRAM™ Self-Refresh DRAM Distinctive Characteristics HyperRAM™ Low Signal Count Interface ■ 3.0 V I/O, 11 bus signals ❐ Single ended clock (CK) ■ 1.8 V I/O, 12 bus signals ❐ Differential clock (CK, CK#) ■ Chip Select (CS#) ■ 8-bit data bus (DQ[7:0]) ■ Read-Write Data Strobe (RWDS) ❐ Bidirectional Data Strobe / Mask ❐ Output at the start of all transactions to indicate refresh latency ❐ Output during read transactions as Read Data Strobe ❐ Input during write transactions as Write Data Mask ■ RWDS DCARS Timing ❐ During read transactions RWDS is offset by a second clock, phase shifted from CK ❐ The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye High Performance ■ Up to 333 MBps ■ Double-Data Rate (DDR) - two data transfers per clock ■ 166 MHz clock rate (333 MBps) at 1.8 V VCC ■ 100 MHz clock rate (200 MBps) at 3.0 V VCC ■ Sequential burst transactions ■ Configurable Burst Characteristics ❐ Wrapped burst lengths: 16 bytes (8 clocks) 32 bytes (16 clocks) 64 bytes (32 clocks) 128 bytes (64 clocks) ❐ Linear burst ❐ Hybrid option - one wrapped burst followed by linear burst ❐ Wrapped or linear burst type selected in each transaction ❐ Configurable output drive strength ■ Low Power Modes ❐ Deep Power Down ■ Package ❐ 24-ball FBGA Performance S...