N-CHANNEL MICROPROCESSOR. 8080A Datasheet

8080A MICROPROCESSOR. Datasheet pdf. Equivalent

8080A Datasheet
Recommendation 8080A Datasheet
Part 8080A
Description 8-BIT N-CHANNEL MICROPROCESSOR
Feature 8080A; infel.. 8080A/8080A-1/8080A-2 8-BIT N-CHANNEL MICROPROCESSOR • TTL Drive Capability • 2,..,s (-1:.
Manufacture Intel
Datasheet
Download 8080A Datasheet




Intel 8080A
infel..
8080A/8080A-1/8080A-2
8-BIT N-CHANNEL MICROPROCESSOR
TTL Drive Capability
2,..,s (-1:1.3,..,s, -2:1.5 ,..,s) Instruction
Cycle
Powerful Problem Solving Instruction
Set
6 General Purpose Registers and an
Accumulator
16-Blt Program Counter for Directly
Addressing up to 64K Bytes of Memory
16-Blt Stack Pointer and Stack
Manipulation Instructions for Rapid
Switching of the Program Environment
Decimal, Binary, and Double Precision
Arithmetic
Ability to Provide Priority Vectored
Interrupts
512 Directly Addressed 110 Ports
Available In EXPRESS
- Standard Temperature Range
Available In 4Q-Lead Cerdlp and Plastic
Packages
(See Packaging Spec. Order #231369)
The Intel 8080A is a complete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip
using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control
and processing applications.
The 8080A contains 6 8-bit general purpose working registers and an accumulator. The 6 general purpose
registers may be addressed individually or in pairs providing both single and double precision operators.
Arithmetic and logical instructions set or reset 4 testable flags. A fifth flag provides decimal arithmetic opera-
tion.
The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out
stack to store/retrieve the contents of the accumulator, flags, program counter, and all of the 6 general
purpose registers. The 16-bit stack pointer controls the addressing of this external stack. This stack gives the
8080A the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor
status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-lIne address and 8-line
bidirectional data busses are used to facilitate easy interface to memory and I/O. Signals to control the
interface to memory and I/O are provided directly by the 8080A. Ultimate control of the address and data
busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the
address and data busses into a high impedance state. This permits OR-tying these busses with other control-
ling devices for (OMA) direct memory access or multi-processor operation.
NOTE:
The 8080A is functionally and electrically compatible with the Intel 8080.
November 1988
1-1 Order Number. 231453-001
This Material Copyrighted By Its Respective Manufacturer



Intel 8080A
intel~
8080A/8080A-1/8080A-2
118'"
INTERNAL DATA BUS
t--""::'''--:::+--~''-'':'Il::4
..fGIIT."
..RUY
TIMING
....0
CONTROL
ACII
Figure 1. Block Diagram
AO"D'.-lO..'._""
A,.
GNO
O.
D.
O.
°7
0.
0,
0,0
D.
-SV
RESET
HOLO
'NT
"INTE 0
OBIN
WR
SYNC
+SV
A"
A,.
Au
Au
At.
"-
"-
At
"-
As
Ao
'"+IN
A,
A,
Ao
.,WAIT
RfADY
HLDA
Figure 2. Pin Configuration
231453-2
231453-1
1-2
This Material Copyrighted By Its Respective Manufacturer



Intel 8080A
intel"
8080A/8080A-1/8080A-2
Symbol
A15-AO
07-0 0
SYNC
OBIN
READY
WAIT
WR
HOLD
HLDA
INTE
INT
RESET1
Vss
Voo
Vee
Vss
(Pt, <1>2
Type
0
I/O
0
0
I
0
0
I
0
0
I
I
Table 1. Pin Description
Name and Function
ADDRESS BUS: The address bus provides the address to memory (up to 64K B-bit
words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao
is the least significant address bit.
DATA BUS: The data bus provides bi-directional communication between the CPU,
memory, and I/O devices for instructions and data transfers. Also, during the first clock
cycle of each machine cycle, the 80BOA outputs a status word on the data bus that
describes the current machine cycle. Do is the least significant bit.
SYNCHRONIZING SIGNAL: The SYNC pin provides a signal to indicate the beginning
of each machine cycle.
DATA BUS IN: The OBIN signal indicates to external circuits that the data bus is in the
input mode. This signal should be used to enable the gating of data onto the B080A data
bus from memory or I/O.
READY: The READY signal indicates to the B080A that valid memory or input data is
available on the BOBOA data bus. This signal is used to synchronize the CPU with slower
memory or I/O devices. If after sending an address out the BOBOA does not receive a
READY input, the 80BOA will enter a WAIT state for as long as the READY line is low.
READY can also be used to single step the CPU.
WAIT: The WAIT signal acknowledges that the CPU is in a WAIT state.
WRITE: The WR signal is used for memory WRITE or I/O output control. The data on
the data bus is stable while the WR signal is active low (WR = 0).
HOLD: The HOLD signal requests the CPU to enter the HOLD state. The HOLD state
allows an external device to gain control of the BOBOA address and data bus as soon as
the 80BOA has completed its use of these busses for the current machine cycle. It is
recognized under the folloWing conditions:
• the CPU is in the HALT state.
• the CPU is in the T2 or TW state and the READY signal is active. As a result of
entering the HOLD state the CPU ADDRESS BUS (A15-AO) and DATA BUS (D7-00)
will be in their high impedance state. The CPU acknowledges its state with the HOLD
ACKNOWLEDGE (HLDA) pin.
HOLD ACKNOWLEDGE: The HlDA signal appears in response to the HOLD signal and
indicates that the data and address bus will go to the high impedance state. The HLDA
signal begins at:
• T3 for READ memory or input.
• The Clock Period following T3 for WRITE memory or OUTPUT operation.
In either case, the HLOA signal appears after the rising edge of <1>2'
INTERRUPT ENABLE: Indicates the content of the internal interrupt enable flip/flop.
This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and
inhibits interrupts from being accepted by the CPU when it is reset. It is automatically
reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M1) when an
interrupt is accepted and is also reset by the RESET signal.
INTERRUPT REQUEST: The CPU recognizes an interrupt request on this line at the end
of the current instruction or while halted. If the CPU is in the HOLD state or if the
Interrupt Enable flip/flop is reset it will not honor the request.
RESET: While the RESET signal is activated, the content of the program counter is
cleared. After RESET, the program will start at location 0 in memory. The INTE and
HLDA flip/flops are also reset. Note that the flags, accumulator, stack pointer, and
registers are not cleared.
GROUND: Reference.
POWER: +12 ±5% V.
POWER: +5 ±5% V.
POWER: - 5 ± 5% V.
CLOCK PHASES: 2 externally supplied clock phases. (non TTL compatible)
NOTE:
1. The RESET signal must be active for a minimum of 3 clock cycles.
1-3
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