Document
dsPIC33CK256MP508 FAMILY
28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD)
Operating Conditions
• 3.0V to 3.6V, -40°C to +85°C, DC to 100 MIPS • 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS
Core: 16-Bit dsPIC33CK CPU
• 32-256 Kbytes of Program Flash with ECC and 8-24K RAM
• Fast 6-Cycle Divide • LiveUpdate • Code Efficient (C and Assembly) Architecture • 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle, Mixed-Sign MUL Plus
Hardware Divide • 32-Bit Multiply Support • Four Sets of Interrupt Context Saving Registers
which Include Accumulator and STATUS for Fast Interrupt Handling • Zero Overhead Looping • RAM Memory Built-In Self-Test (MBIST)
Clock Management
• Internal Oscillator • Programmable PLLs and Oscillator Clock Sources • Reference Clock Output • Fail-Safe Clock Monitor (FSCM) • Fast Wake-up and Start-up • Backup Internal Oscillator
Power M.