R6511Q

'1'Rockwell R6511Q R6500/13 R6500 Microcomputer System R6511Q One-Chip Microprocessor and R6500/13 One-Chip Microcomputer SECTION 1 INTRODUCTION 1.1 FEATURES Enhanced 6502 CPU -Four new bit manipulation instructions Set Memory Bit (SMB) Reset Memory Bit (RMB) Branch on Bit Set (BBS) Branch on Bit Reset (BBR) -Decimal and binary arithmetic modes -13 addressing modes -True indexing 256-byte.mask-programmable ROM or no ROM' 192-byte static RAM 32 bidirectional, TIL-compatible I/O lines (four ports) One 8-bit port may be tri-stated under software control One 8-bit port may have latched inputs under software control Two 16-bit programmable counter/timers, with latches -Pulse width measurement -Asymmetrical pulse generation -Pulse generation -Interval timer -Event counter -Retriggerable interval timer Serial port -Full-duplex asynchronous operation mode -Selectable 5- to 8-bit characters -Wake-up feature -Synchronous shift register mode ...