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IS25LP080D Dataheets PDF



Part Number IS25LP080D
Manufacturers ISSI
Logo ISSI
Description SERIAL FLASH MEMORY
Datasheet IS25LP080D DatasheetIS25LP080D Datasheet (PDF)

IS25LP080D IS25WP080D IS25WP040D IS25WP020D 8/4/2Mb SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE DATA SHEET 8/4/2Mb SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE IS25LP080D IS25WP080D/040D/020D FEATURES  Industry Standard Serial Interface - IS25LP080D: 8Mbit/1Mbyte - IS25WP080D: 8Mbit/1Mbyte - IS25WP040D: 4Mbit/512Kbyte - IS25WP020D: 2Mbit/256Kbyte - 256 bytes per Programmable Page - Supports standard SPI, Fast, Dual, Dual I/O, Qu.

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IS25LP080D IS25WP080D IS25WP040D IS25WP020D 8/4/2Mb SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE DATA SHEET 8/4/2Mb SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE IS25LP080D IS25WP080D/040D/020D FEATURES  Industry Standard Serial Interface - IS25LP080D: 8Mbit/1Mbyte - IS25WP080D: 8Mbit/1Mbyte - IS25WP040D: 4Mbit/512Kbyte - IS25WP020D: 2Mbit/256Kbyte - 256 bytes per Programmable Page - Supports standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI - Supports Serial Flash Discoverable Parameters (SFDP)  High Performance Serial Flash (SPI) - 50MHz Normal and 133Mhz Fast Read - 532 MHz equivalent QPI - DTR (Dual Transfer Rate) up to 66MHz - Selectable Dummy Cycles - Configurable Drive Strength - Supports SPI Modes 0 and 3 - More than 100,000 Erase/Program Cycles - More than 20-year Data Retention  Flexible & Efficient Memory Architecture - Chip Erase with Uniform: Sector/Block Erase (4/32/64 Kbyte) - Program 1 to 256 Bytes per Page - Program/Erase Suspend & Resume  Efficient Read and Program modes - Low Instruction Overhead Operations - Continuous Read 8/16/32/64-Byte Burst Wrap - Selectable Burst Length - QPI for Reduced Instruction Overhead - AutoBoot Operation  Low Power with Wide Temp. Ranges - Single Voltage Supply IS25LP: 2.30V to 3.60V IS25WP: 1.65V to 1.95V - 10 mA Active Read Current - 8 µA Standby Current - 1 µA Deep Power Down - Temp Grades: Extended: -40°C to +105°C Auto Grade (A3): -40°C to +125°C  Advanced Security Protection - Software and Hardware Write Protection - Power Supply Lock Protect - 4x256-Byte Dedicated Security Area with OTP User-lockable Bits - 128 bit Unique ID for Each Device (Call Factory)  Industry Standard Pin-out & Packages(1) - B = 8-pin SOIC 208mil - N = 8-pin SOIC 150mil - V = 8-pin VVSOP 150mil - K = 8-contact WSON 6x5mm - U = 8-contact USON 2x3mm - T = 8-contact USON 4x3mm (Call Factory) - KGD (Call Factory) Notes: 1. Call Factory for other package options available Integrated Silicon Solution, Inc.- www.issi.com Rev. B8 07/18/2019 2 GENERAL DESCRIPTION IS25LP080D IS25WP080D/040D/020D The IS25LP080D and IS25WP080D/040D/020D Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions). The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation. Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory. QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention. GLOSSARY Standard SPI In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions, addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the status of the device. This device supports SPI bus operation modes (0, 0) and (1, 1). Multi I/O SPI Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations. QPI The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can signifi.


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