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IS62WVS5128GBLL Dataheets PDF



Part Number IS62WVS5128GBLL
Manufacturers ISSI
Logo ISSI
Description FAST SERIAL SRAM
Datasheet IS62WVS5128GBLL DatasheetIS62WVS5128GBLL Datasheet (PDF)

IS62/65WVS5128GALL IS62/65WVS5128GBLL 512Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE JULY 2021 KEY FEATURES • SPI-Compatible Bus Interface: - 30/45 MHz Clock rate - SPI/SDI/SQI mode • Single Power Supply: - VDD = 1.65V - 2.2V (IS62/65WVS5128GALL) - VDD = 2.70V - 3.6V (IS62/65WVS5128GBLL) • Read Latency: - SPI mode: 8 clocks - DPI mode: 4 clocks - QPI mode: 2 clocks • Low-Power CMOS Technology: - Read Current: 20 mA(max) at 3.6V, 45 MHz, 85°C - CMOS Standby Current: 8.

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IS62/65WVS5128GALL IS62/65WVS5128GBLL 512Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE JULY 2021 KEY FEATURES • SPI-Compatible Bus Interface: - 30/45 MHz Clock rate - SPI/SDI/SQI mode • Single Power Supply: - VDD = 1.65V - 2.2V (IS62/65WVS5128GALL) - VDD = 2.70V - 3.6V (IS62/65WVS5128GBLL) • Read Latency: - SPI mode: 8 clocks - DPI mode: 4 clocks - QPI mode: 2 clocks • Low-Power CMOS Technology: - Read Current: 20 mA(max) at 3.6V, 45 MHz, 85°C - CMOS Standby Current: 8 A(typ) • 512K x 8-bit Organization: - 32-byte page • Byte, Page and Sequential mode for Reads and Writes • Temperature Ranges Supported: - Industrial (I): -40C to +85C - Automotive (A3): -40C to +125C • RoHS Compliant - 8-pin SOIC package DESCRIPTION The ISSI IS62/65WVS5128GALL/GBLL are 4M bit Fast Serial static RAMs organized as 512K bytes by 8 bits. It is a dual die stack of two 2Mb Serial SRAMs. The device is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access the device is controlled through a Chip Select (CS#) input. Additionally, SDI (Serial Dual Interface) and SQI (Serial Quad Interface) is supported if your application needs faster data rates. This device also supports unlimited reads and writes to the memory array. The IS62/65WVS5128GALL/GBLL are available in the standard 8-pin SOIC package. Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. A9 07/06/2021 IS62/65WVS5128GALL IS62/65WVS5128GBLL BLOCK DIAGRAM SI (SIO0) SO (SIO1) DNU (SIO2) HOLD# (SIO3) CS# SCK SI (SIO0) SO (SIO1) Die 0 DNU (SIO2) HOLD# (SIO3) CS# SCK VSS VDD VSS VDD SI (SIO0) SO (SIO1) Die 1 DNU (SIO2) HOLD# (SIO3) CS# SCK VSS VDD Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A9 07/06/2021 IS62/65WVS5128GALL IS62/65WVS5128GBLL PIN CONFIGURATIONS 8-pin SOIC CS# 1 SO(SIO1) 2 DNU(SIO2) 3 VSS 4 PIN DESCRIPTIONS CS# Chip Enable Input 8 VDD SO/SIO1 DNU/SIO2 Serial Output/SIO1 Do Not Use/SIO2 VSS 7 HOLD# (SIO3) SI/SIO0 Ground Serial Input/SIO0 SCK Serial Clock 6 SCK HOLD#/SIO3 HOLD#/SIO3 VDD Power 5 SI (SIO0) Integrated Silicon Solution, Inc.- www.issi.com 3 Rev. A9 07/06/2021 IS62/65WVS5128GALL IS62/65WVS5128GBLL Chip Select (CS#) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. When the device is deselected, SO goes to the high- impedance state, allowing multiple parts to share the same SPI bus. After power-up, a low level on CS# is required, prior to any sequence being initiated. Serial Clock (SCK) The SCK is used to synchronize the communication between a master and Serial SRAM. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. Serial Output (SO: SPI mode) The SO pin is used to transfer data out of the device. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. Serial Input (SI: SPI mode) The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock. HOLD Function (HOLD#: SPI Mode, and SDI Mode) The HOLD# pin is used to suspend transmission to Serial SRAM while in the middle of a serial sequence without having to re-transmit the entire sequence over again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD# pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD# pin should be brought low while SCK is low, otherwise the HOLD function will not be invoked until the.


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