PRMD3
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors
(RET)
14 September 2018
Product data sheet
1. Gener...
PRMD3
50 V, 100 mA
NPN/
PNP Resistor-Equipped double
Transistors
(RET)
14 September 2018
Product data sheet
1. General description
NPN/
PNP Resistor-Equipped double
Transistors (RET) in a leadless ultra small DFN1412-6 (SOT1268) leadless Surface-Mounted Device (SMD) plastic package.
NPN/
NPN complement: PRMH11;
PNP/
PNP complement: PRMB11.
2. Features and benefits
100 mA output current capability Built-in bias resistors Simplifies circuit design Reduces component count Reduces pick and place costs Low package height of 0.5 mm AEC-Q101 qualified
3. Applications
Digital applications Cost-saving alternative to BC847/BC857 series in digital applications Control of IC inputs Switching loads
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Conditions
Per
transistor, for the
PNP transistor with negative polarity
VCEO
collector-emitter voltage
open base
IO hFE R1 R2/R1
output current DC current gain bias resistor 1...
