Document
September 2006 Advance Information
AS7C31025C
®
3.3V 128K X 8 CMOS SRAM (Center power and ground)
A9 A10 A11 A12 A13 A14 A15 A16
Features
• Industrial and commercial temperatures • Organization: 131,072 x 8 bits • High speed
- 10 ns address access time - 5 ns output enable access time • Low power consumption via ship deselect • Easy memory expansion with CE, OE inputs • Center power and ground • TTL/LVTTL-compatible, three-state I/O • JEDEC-standard packages
Logic block diagram
VCC GND
A0 A1 A2 A3 A4 A5 A6 A7 A8
Address decoder Sense amp
Input buffer
131,072 x 8 Array
(1,048,576)
I/O7 I/O0
Address decoder
Control circuit
WE
OE CE
- 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ - 32-pin, TSOP 2 • ESD protection ≥ 2000 volts
Pin arrangement
32-pin TSOP 2
A0 A1 A2 A3
CE I/O0 I/O1 VCC GND I/O2 I/O3 WE
A4 A5 A6
A7
1
2 3 4
5 6 7 8 9
10 11 12
13 14 15 16
AS7C31025C
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24 23
VCC I/O5
22 I/O4
2.