9ZXL0651E Data Sheet PDF | IDT





(Datasheet) 9ZXL0651E PDF Download

Part Number 9ZXL0651E
Description 6-Output DB800ZL Derivative
Manufacture IDT
Total Page 20 Pages
PDF Download Download 9ZXL0651E Datasheet PDF

Features: 6-Output DB800ZL Derivative for PCIe Gen 1–4 and UPI 9ZXL0631E / 9ZXL0651E Da tasheet Description The 9ZXL0631E / 9Z XL0651E are second-generation, enhanced -performance DB800ZL derivatives. The p arts are pin-compatible upgrades to the 9ZXL0631A and 9ZXL0651A, while offerin g a much improved phase jitter performa nce. A fixed external feedback maintain s low drift for critical QPI/UPI applic ations. PCIe Clocking Architectures Sup ported ▪ Common Clocked (CC) ▪ Inde pendent Reference (IR) with and without spread spectrum Typical Applications Servers ▪ Storage ▪ JBOD ▪ Net working Output Features ▪ 6 Low-power HCSL (LP-HCSL) output pairs (0631E) 6 Low-power HCSL (LP-HCSL) output pai rs with 85Ω Zout (0651E) Features LP-HCSL outputs; eliminate 12 resisto rs, save 20mm2 of area (0631E) ▪ LP-H CSL outputs with 85Ω Zout; eliminate 24 resistors, save 48mm2 of area (0651E ) ▪ 6 OE# pins; hardware control of e ach output ▪ Selectable PLL BW; minimizes jitter peaking in c.

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9ZXL0651E datasheet
6-Output DB800ZL Derivative
for PCIe Gen1–4 and UPI
9ZXL0631E / 9ZXL0651E
Datasheet
Description
The 9ZXL0631E / 9ZXL0651E are second-generation,
enhanced-performance DB800ZL derivatives. The parts are
pin-compatible upgrades to the 9ZXL0631A and 9ZXL0651A,
while offering a much improved phase jitter performance. A fixed
external feedback maintains low drift for critical QPI/UPI
applications.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Typical Applications
Servers
Storage
JBOD
Networking
Output Features
6 Low-power HCSL (LP-HCSL) output pairs (0631E)
6 Low-power HCSL (LP-HCSL) output pairs with 85Zout
(0651E)
Features
LP-HCSL outputs; eliminate 12 resistors, save 20mm2 of area
(0631E)
LP-HCSL outputs with 85Zout; eliminate 24 resistors, save
48mm2 of area (0651E)
6 OE# pins; hardware control of each output
Selectable PLL BW; minimizes jitter peaking in cascaded PLL
topologies
Hardware/SMBus control of PLL bandwidth and bypass;
change mode without power cycle
Spread spectrum compatible; tracks spreading input clock for
EMI reduction
100MHz PLL Mode; UPI support
5 × 5 mm 40-QFN package; small board footprint
Key Specifications
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
Input-to-output delay: fixed at 0ps
Input-to-output delay variation < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: QPI/UPI > 9.6GB/s < 0.2ps rms
Phase jitter: IF-UPI < 1.0ps rms
Block Diagram
VDDR
VDDA
VDD x9
DIFIN#
DIFIN
PLL
FBOUT_NC#
FBOUT_NC
DIF5#
DIF5
SMBCLK
SMBDAT
^vHIBW_BYPM-LOBW#
^CKPWRGD_PD#
vOE[5:0]#
©2018 Integrated Device Technology, Inc.
SMBus Factory
Engine Configuration
6 outputs
Control Logic
Resistors are integrated on 9ZXL065x
devices and external on 9ZXL063x devices
GNDR
EPAD/GND
DIF0#
DIF0
1
November 30, 2018

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