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M12L64164A-5TG2Y Data Sheet

1M x 16 Bit x 4 Banks Synchronous DRAM

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M12L64164A-5TG2Y
ESMT SDRAM FEATURES y JEDEC standard 3.3V power supply y LVTTL compatible with multiplexed address y Four banks operation y MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) y All inputs are sampled at the positive going edge of the system clock y DQM for masking y Auto & self refresh y 64ms refresh period (4K cycle) - 15.6 μ s refresh interval M12L64164A (2Y) 1M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID Max Freq. Package Comments M12L64164A-5TG2Y 200MHz 54 TSOP II Pb-free M12L64164A-6TG2Y 166MHz 54 TSOP II Pb-free M12L64164A-7TG2Y M12L64164A-5BG2Y M12L64164A-6BG2Y M12L64164A-7BG2Y 143MHz 200MHz 166MHz 143MHz 54 TSOP II 54 VBGA 54 VBGA 54 VBGA Pb-free Pb-free Pb-free Pb-free GENERAL DESCRIPTION The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows precise cycle controls wit.
M12L64164A-5TG2Y

Download M12L64164A-5TG2Y Datasheet
ESMT SDRAM FEATURES y JEDEC standard 3.3V power supply y LVTTL compatible with multiplexed address y Four banks operation y MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) y All inputs are sampled at the positive going edge of the system clock y DQM for masking y Auto & self refresh y 64ms refresh period (4K cycle) - 15.6 μ s refresh interval M12L64164A (2Y) 1M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID Max Freq. Package Comments M12L64164A-5TG2Y 200MHz 54 TSOP II Pb-free M12L64164A-6TG2Y 166MHz 54 TSOP II Pb-free M12L64164A-7TG2Y M12L64164A-5BG2Y M12L64164A-6BG2Y M12L64164A-7BG2Y 143MHz 200MHz 166MHz 143MHz 54 TSOP II 54 VBGA 54 VBGA 54 VBGA Pb-free Pb-free Pb-free Pb-free GENERAL DESCRIPTION The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows precise cycle controls wit.


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