M12L64322A-5TG2S

ESMT SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L64322A (2S) 512K x 32 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID Max Freq. Package Comments M12L64322A-5TG2S 200MHz 86 TSOPII Pb-free M12L64322A-6TG2S 166MHz 86 TSOPII Pb-free M12L64322A-7TG2S 143MHz 86 TSOPII Pb-free M12L64322A-5BG2S 200MHz 90 BGA Pb-free M12L64322A-6BG2S 166MHz 90 BGA Pb-free M12L64322A-7BG2S 143MHz 90 BGA Pb-free GENERAL DESCRIPTION The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits. Synchronous design allows precise cycle control with the...