Document
ESMT
SDRAM
FEATURES
y JEDEC standard 3.3V power supply y LVTTL compatible with multiplexed address y Four banks operation y MRS cycle with address key programs
- CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) y All inputs are sampled at the positive going edge of the system clock y Burst Read single write operation y DQM for masking y Auto & self refresh y 64ms refresh period (4K cycle)
M12L128168A (2N)
2M x 16 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
Product ID
M12L128168A-5TG2N M12L128168A-5BG2N M12L128168A-6TG2N M12L128168A-6BG2N M12L128168A-7TG2N M12L128168A-7BG2N
Max Freq.
Package Comments
200MHz 54 Pin TSOPII Pb-free
200MHz 54 Ball FBGA Pb-free
166MHz 54 Pin TSOPII Pb-free
166MHz 54 Ball FBGA Pb-free
143MHz 54 Pin TSOPII Pb-free
143MHz 54 Ball FBGA Pb-free
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchr.