M12L128324A-7TG2C

ESMT SDRAM FEATURES  JEDEC standard 3.3V power supply  LVTTL compatible with multiplexed address  Four banks operation  MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave)  All inputs are sampled at the positive going edge of the system clock  DQM for masking  Auto & self refresh  64ms refresh period (4K cycle) M12L128324A (2C) 1M x 32 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L128324A-5TG2C M12L128324A-6TG2C M12L128324A-7TG2C Max Freq. Package Comments 200MHz 86 TSOPII Pb-free 166MHz 86 TSOPII Pb-free 143MHz 86 TSOPII Pb-free GENERAL DESCRIPTION The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengt...