M12L32162A-7TG

ESMT Preliminary Revision History Revision 0.1 (Aug. 11 2006) - Original Revision 0.2 (Mar. 20 2007) - Add BGA package Revision 0.3 (Apr. 27 2007) - Rename BGA pin name (BA1 to NC; BA0 to BA) - Modify DC Characteristics www.DataSheet4U.com M12L32162A Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2007 Revision : 0.3 1/29 ESMT SDRAM Preliminary M12L32162A 1M x 16Bit x 2Banks Synchronous DRAM FEATURES z JEDEC standard 3.3V power supply z LVTTL compatible with multiplexed address z Dual banks operation z MRS cycle with address key programs - CAS Latency (2 & 3 ) www.DataSheet4U-.comBurst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) z All inputs are sampled at the positive going edge of the system clock z Burst Read Single-bit Write operation z DQM for masking z Auto & self refresh z 64ms refresh period (4K cycle) GENERAL DESCRIPTION The M12L32162A is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 x 1,048,576 ...