2M x 16 Bit x 4 Banks Synchronous DRAM
ESMT
SDRAM
FEATURES
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operatio...
Description
ESMT
SDRAM
FEATURES
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs
- CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh (self refresh is not supported for VA grade) Refresh - 64 ms refresh period (4K cycle) for V grade -16 ms refresh period (4K cycle) for VA grade
M12L128168A (2S)
Automotive Grade
2M x 16 Bit x 4 Banks
Synchronous DRAM
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable la...
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