F50L2G41XA-104YG2B

ESMT Flash (Preliminary) F50L2G41XA (2B) 3.3V 2 Gbit SPI-NAND Flash Memory FEATURES  Single-level cell (SLC) technology  Organization - Page size x1: 2176 bytes (2048 + 128 bytes) - Block size: 64 pages (128K + 8K bytes) - Plane size: 2Gb (2 planes, 1024 blocks per plane)  Standard and extended SPI-compatible serial bus interface - Instruction, address on 1 pin; data out on 1, 2, or 4 pins - Instruction on 1 pin; address, data out on 2 or 4 pins - Instruction, address on 1 pin; data in on 1 or 4 pins  User-selectable internal ECC supported - 8 bits/sector  Array performance - 104 MHz clock frequency (MAX) - Page read: 25μs (MAX) with on-die ECC disabled; 70μs (MAX) with on-die ECC enabled - Page program: 200μs (TYP) with on-die ECC disabled; 220μs (TYP) with on-die ECC enabled - Block erase: 2ms (TYP)  Advanced features - Read page cache mode - Read unique ID - Read parameter page  Device initialization - Automatic device initialization after power-up  S...