(PDF) 83947 Datasheet PDF | IDT





83947 Datasheet PDF

Part Number 83947
Description LVCMOS Fanout Buffer
Manufacture IDT
Total Page 10 Pages
PDF Download Download 83947 Datasheet PDF

Features: Datasheet pdf Low Skew, 1-to-9 LVCMOS Fanout Buffer 8 3947 Data Sheet GENERAL DESCRIPTION Th e 83947I is a low skew, 1-to-9 LVCMOS F anout Buffer. The low impedance LVCMOS/ LVTTL outputs are designed to drive 50 series or parallel terminated transmi ssion lines. The effective fanout can b e increased from 9 to 18 byutilizing th e ability of the outputs to drive two s eries terminated lines. Guaranteed outp ut and part-to-part skew characteristic s make the 83947I ideal for high perfor mance, single ended applications that a lso require a limited output voltage. FEATURES • 9 LVCMOS/LVTTL outputs • Selectable CLK0 and CLK1 can accept th e following input levels: LVCMOS and LV TTL • Maximum output frequency: 110MH z • Output skew: 500ps (maximum) • Part-to-part skew: 2ns (maximum) • 3. 3V operating supply • -40°C to 85°C ambient operating temperature • Lead -Free package available BLOCK DIAGRAM ©2016 Integrated Device Technology, In c PIN ASSIGNMENT GND Q2 VDDO Q1 GND Q0 VDDO GND 32 31 30 29 .

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83947 datasheet
Low Skew, 1-to-9
LVCMOS Fanout Buffer
83947
Data Sheet
GENERAL DESCRIPTION
The 83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer. The low
impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series
or parallel terminated transmission lines. The effective fanout can be
increased from 9 to 18 byutilizing the ability of the outputs to drive two
series terminated lines.
Guaranteed output and part-to-part skew characteristics make the
83947I ideal for high performance, single ended applications that also
require a limited output voltage.
FEATURES
9 LVCMOS/LVTTL outputs
Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
Maximum output frequency: 110MHz
Output skew: 500ps (maximum)
Part-to-part skew: 2ns (maximum)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Lead-Free package available
BLOCK DIAGRAM
©2016 Integrated Device Technology, Inc
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
VDD
GND
1 24
2 23
3 22
4 ICS83947I 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
GND
Q3
VDDO
Q4
GND
Q5
VDDO
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
1 Revision B March 17, 2016

83947 datasheet
83947 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 8, 9, 12, 16, 17, 20,
24, 25, 29, 32
GND
Power
Power supply ground.
2
CLK_SEL
Input
Pullup
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
3, 4
CLK0, CLK1
Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
5
CLK_EN
Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels.
7
10, 14, 18, 22, 27, 31
11, 13, 15, 19, 21, 23,
26, 28, 30
VDD Power
VDDO
Power
Q8, Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output
Coree supply pin.
Output supply pins.
Q0 thru Q8 clock outputs.
LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
CPD
RPULLUP
RPULLDOWN
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum Typical Maximum Units
4 pF
25 pF
51 KΩ
51 KΩ
5 7 12 Ω
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
OE CLK_EN
0X
10
11
Output
Q0:Q8
Hi-Z
LOW
Follows CLK input
©2016 Integrated Device Technology, Inc
2
Revision B March 17, 2016




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