9ZML1252E Datasheet: 2:12 DB1200ZL Derivative





9ZML1252E 2:12 DB1200ZL Derivative Datasheet

Part Number 9ZML1252E
Description 2:12 DB1200ZL Derivative
Manufacture IDT
Total Page 19 Pages
PDF Download Download 9ZML1252E Datasheet PDF

Features: 2:12 DB1200ZL Derivative for PCIe Gen1 4 and UPI 9ZML1232E / 9ZML1252E Datas heet Description The 9ZML1232E / 9ZML1 252E are a second generation 2-input/12 -output differential mux for Intel Purl ey and newer platforms. It exceeds the demanding DB1200ZL performance specific ations and is backwards compatible to t he 9ZML1232B. It utilizes Low-Power HCS L-compatible outputs to reduce power co nsumption and termination resistors. It is suitable for PCI-Express Gen1–4 o r QPI/UPI applications, and provides 2 configurable low-drift I2O settings, on e for each input channel, to allow I2O tuning for various topologies. PCIe Clo cking Architectures Supported ▪ Commo n Clocked (CC) ▪ Separate Reference N o Spread (SRNS) ▪ Separate Reference Independent Spread (SRIS) Typical Appli cations Servers, Storage, Networking, S SDs Output Features ▪ 12 Low-power HC SL (LP-HCSL) output pairs (9ZML1232E) 12 Low-power HCSL (LP-HCSL) output p airs with 85Ω Zout (9ZML1252E) Block Diagram Features ▪ 2 .

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2:12 DB1200ZL Derivative for
PCIe Gen1–4 and UPI
9ZML1232E / 9ZML1252E
Datasheet
Description
The 9ZML1232E / 9ZML1252E are a second generation
2-input/12-output differential mux for Intel Purley and newer
platforms. It exceeds the demanding DB1200ZL performance
specifications and is backwards compatible to the 9ZML1232B. It
utilizes Low-Power HCSL-compatible outputs to reduce power
consumption and termination resistors. It is suitable for PCI-Express
Gen1–4 or QPI/UPI applications, and provides 2 configurable
low-drift I2O settings, one for each input channel, to allow I2O tuning
for various topologies.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Separate Reference No Spread (SRNS)
Separate Reference Independent Spread (SRIS)
Typical Applications
Servers, Storage, Networking, SSDs
Output Features
12 Low-power HCSL (LP-HCSL) output pairs (9ZML1232E)
12 Low-power HCSL (LP-HCSL) output pairs with 85Zout
(9ZML1252E)
Block Diagram
Features
2 configurable low drift I2O delays up to 2.9ns; maintain transport
delay for various topologies
LP-HCSL outputs; eliminate 24 resistors (9ZML1232E)
LP-HCSL outputs with Zout = 85; eliminate 48 resistors
(9ZML1252E)
9 selectable SMBus addresses; multiple devices can share same
SMBus segment
Separate VDDIO for outputs; allows maximum power savings
PLL or Bypass Mode; PLL can dejitter incoming clock
Hardware or software-selectable PLL BW; minimizes jitter
peaking in downstream PLLs
Spread spectrum compatible; tracks spreading input clock for EMI
reduction
SMBus interface; software can modify device settings without
hardware changes
10 x 10 mm 72-QFN package; small board footprint
Key Specifications
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50ps
Input-to-output delay: Fixed at 0 ps
Input-to-output delay variation < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: UPI > 9.6GB/s < 0.1ps rms
^SEL_A_B#
DIF_INA
DIF_INB
^vHIBW_BYPM
_LOBW#
CKPWRGD_PD#
vSMB_A0_tri
vSMB_A1_tri
SMBDAT
SMBCLK
^OE(11:0)#
I2O
Delay
Low Phase
Noise Z-PLL
(SS-
Compatible)
Bypass path
NOTE: Internal series resistors are
only present on the 9ZML1252
FBOUT_NC
DIF_11
12
outputs
DIF_0
©2018 Integrated Device Technology, Inc
1
April 12, 2018

                    
                    






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