9ZML1253E Datasheet: 2:12 DB1200ZL Derivative





9ZML1253E 2:12 DB1200ZL Derivative Datasheet

Part Number 9ZML1253E
Description 2:12 DB1200ZL Derivative
Manufacture IDT
Total Page 24 Pages
PDF Download Download 9ZML1253E Datasheet PDF

Features: 2:12 DB1200ZL Derivative for PCIe Gen1-4 and UPI 9ZML1233E / 9ZML1253E Datashe et Description The 9ZML1233E / 9ZML125 3E are second generation enhanced perfo rmance DB1200ZL derivatives. The parts are pin-compatible upgrades to the 9ZML 1232B, while offering much improved pha se jitter performance. A fixed external feedback maintains low drift for criti cal QPI/UPI applications, while each in put channel has software adjustable inp ut-to-output delay to ease transport de lay management for today's more complex server topologies. The 9ZML1233E and 9 ZML1253E have an SMBus Write Lockout pi n for increased device and system secur ity. PCIe Clocking Architectures Suppor ted ▪ Common Clocked (CC) ▪ Indepen dent Reference (IR) with and without sp read spectrum Typical Applications ▪ Servers ▪ Storage ▪ Networking ▪ SSDs Output Features ▪ 12 Low-Power ( LP) HCSL output pairs (1233E) ▪ 12 Lo w-Power (LP) HCSL output pairs with 85 Zout (1253E) Block Diagram Features ▪ SMBus write lock fe.

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2:12 DB1200ZL Derivative for
PCIe Gen1-4 and UPI
9ZML1233E / 9ZML1253E
Datasheet
Description
The 9ZML1233E / 9ZML1253E are second generation enhanced
performance DB1200ZL derivatives. The parts are pin-compatible
upgrades to the 9ZML1232B, while offering much improved phase
jitter performance. A fixed external feedback maintains low drift for
critical QPI/UPI applications, while each input channel has software
adjustable input-to-output delay to ease transport delay
management for today's more complex server topologies. The
9ZML1233E and 9ZML1253E have an SMBus Write Lockout pin for
increased device and system security.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Typical Applications
Servers
Storage
Networking
SSDs
Output Features
12 Low-Power (LP) HCSL output pairs (1233E)
12 Low-Power (LP) HCSL output pairs with 85Zout (1253E)
Block Diagram
Features
SMBus write lock feature; increases system security
2 software-configurable input-to-output delay lines; manage
transport delay for complex topologies
LP-HCSL outputs; eliminate 24 resistors, save 41mm2 of area
(1233E)
LP-HCSL outputs with 85Zout; eliminate 48 resistors, save
82mm2 of area (1253E)
12 OE# pins; hardware control of each output
3 selectable SMBus addresses; multiple devices can share same
SMBus segment
Selectable PLL bandwidths; minimizes jitter peaking in cascaded
PLL topologies
Hardware/SMBus control of PLL bandwidth and bypass; change
mode without power cycle
Spread spectrum compatible; tracks spreading input clock for EMI
reduction
100MHz PLL Mode; UPI support
10 x 10 mm 72-VFQFPN package; small board footprint
Key Specifications
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50ps
Input-to-output delay: 0ps default
Input-to-output delay variation < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: UPI > 9.6GB/s < 0.1ps rms
Phase jitter: IF-UPI < 1.0ps rms
^SEL_A_B#
DIF_INA
DIF_INA
DIF_INB
DIF_INB
^vHIBW_BYPM_LOBW#
CKPWRGD_PD#
vSMB_A0_tri
vSMB_WRTLOCK
SMBDAT
SMBCLK
^OE(11:0)#
I2O
Delay
©2018 Integrated Device Technology, Inc.
Low Phase Noise
Z-PLL
(SS-Compatible)
Bypass path
NOTE: Internal series resistors are only
present on the 9ZML1253
1
12
outputs
FBOUT_NC
FBOUT_NC
DIF_11
DIF_11
DIF_0
DIF_0
April 12, 2018

                    
                    






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