9ZXL0451E Datasheet: 4-Output DB800ZL Derivative





9ZXL0451E 4-Output DB800ZL Derivative Datasheet

Part Number 9ZXL0451E
Description 4-Output DB800ZL Derivative
Manufacture IDT
Total Page 18 Pages
PDF Download Download 9ZXL0451E Datasheet PDF

Features: 4-Output DB800ZL Derivative for PCIe Gen 1–5, UPI and DB2000Q 9ZXL0451E Datas heet Description The 9ZXL0451E is a se cond generation enhanced performance DB 800ZL derivative for PCIe Gen4 and 5 ap plications. In fanout (bypass) mode, it is DB2000Q compatible. A fixed externa l feedback in ZDB mode maintains low dr ift for critical QPI/UPI applications. PCIe Clocking Architectures Supported Common Clocked (CC) ▪ Independent Reference (IR) with and without spread spectrum Typical Applications ▪ Serve rs ▪ Storage ▪ Networking ▪ eSSDs ▪ PCIe expansion Output Features ▪ 4 Low-power HCSL (LP-HCSL) output pair s with 85Ω Zout Features ▪ LP-HCSL outputs eliminate 16 resistors; save 3 2mm2 of area ▪ 4 OE# pins; SMBus cont rol also available ▪ 3 selectable SMB us addresses ▪ 2 selectable ZDB bandw idths; minimizes jitter peaking in casc aded PLL topologies ▪ Hardware/SMBus control of ZDB bandwidth and fanout mod es ▪ Spread spectrum compatible ▪ 100MHz ZDB mode ▪ 5 × .

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4-Output DB800ZL Derivative for
PCIe Gen1–5, UPI and DB2000Q
9ZXL0451E
Datasheet
Description
The 9ZXL0451E is a second generation enhanced performance
DB800ZL derivative for PCIe Gen4 and 5 applications. In fanout
(bypass) mode, it is DB2000Q compatible. A fixed external
feedback in ZDB mode maintains low drift for critical QPI/UPI
applications.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Typical Applications
Servers
Storage
Networking
eSSDs
PCIe expansion
Output Features
4 Low-power HCSL (LP-HCSL) output pairs with 85Zout
Features
LP-HCSL outputs eliminate 16 resistors; save 32mm2 of area
4 OE# pins; SMBus control also available
3 selectable SMBus addresses
2 selectable ZDB bandwidths; minimizes jitter peaking in
cascaded PLL topologies
Hardware/SMBus control of ZDB bandwidth and fanout modes
Spread spectrum compatible
100MHz ZDB mode
5 × 5 mm 32-VFQFPN package; small board footprint
Key Specifications
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
Input-to-output delay variation (ZDB mode): < 50ps
Phase jitter ZDB mode: PCIe Gen4 < 0.35ps rms
Additive phase Jitter (fanout mode): PCIe Gen4 < 0.05ps rms
Additive phase Jitter (fanout mode): PCIe Gen5 < 0.05ps rms
Additive phase Jitter (fanout mode): DB2000Q < 0.05ps rms
Phase jitter (all modes): UPI > 9.6GB/s < 0.1ps rms
Additive phase jitter (all modes): IF-UPI < 1.0ps rms
Block Diagram
VDDR
VDDA
DIF_IN#
DIF_IN
PLL
VDD x5
FBOUT_NC#
FBOUT_NC
DIF3#
DIF3
vSADR 0_tri
SMBCLK
SMBDAT
SMBus
Factory
Engine Configuration
^HIBW_BYPM-LOBW#
^CKPWRGD _PD#
vOE[3:0]#
Control Logic
©2019 Integrated Device Technology, Inc.
EPAD/GND
1
4
outputs
DIF0#
DIF0
March 4, 2019

                    
                    






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