9ZXL0652E Datasheet PDF | IDT





9ZXL0652E Datasheet PDF Download

Part Number 9ZXL0652E
Description 6-Output DB800ZL Derivative
Manufacture IDT
Total Page 20 Pages
PDF Download Download 9ZXL0652E Datasheet PDF

Features: 6-Output DB800ZL Derivative for PCIe Ge n1–4 and UPI with Write 9ZXL0632E / 9 ZXL0652E Lock Datasheet Description The 9ZXL0632E / 9ZXL0652E second-genera tion, enhanced-performance DB800ZL diff erential buffers. The parts are functio nally compatible to the 9ZXL0632A and 9 ZXL0652A while offering much improved p hase jitter performance. A fixed extern al feedback maintains low drift for cri tical QPI/UPI applications. The 9ZXL063 2E and 9ZXL0652E have an SMBus Write Lo ckout pin for increased device and syst em security. PCIe Clocking Architecture s Supported ▪ Common Clocked (CC) ▪ Independent Reference (IR) with and wi thout spread spectrum Typical Applicati ons ▪ Servers ▪ Storage ▪ JBOD Networking Output Features ▪ 6 Low- power HCSL (LP-HCSL) output pairs (0632 E) ▪ 6 Low-power HCSL (LP-HCSL) outpu t pairs with 85Ω Zout (0652E) Featur es ▪ SMBus write lock feature; increa ses system security ▪ LP-HCSL outputs ; eliminate 12 resistors, save 20mm2 of area (0632E) ▪ LP-HCS.

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9ZXL0652E datasheet
6-Output DB800ZL Derivative for
PCIe Gen1–4 and UPI with Write 9ZXL0632E / 9ZXL0652E
Lock
Datasheet
Description
The 9ZXL0632E / 9ZXL0652E second-generation,
enhanced-performance DB800ZL differential buffers. The parts
are functionally compatible to the 9ZXL0632A and 9ZXL0652A
while offering much improved phase jitter performance. A fixed
external feedback maintains low drift for critical QPI/UPI
applications. The 9ZXL0632E and 9ZXL0652E have an SMBus
Write Lockout pin for increased device and system security.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Typical Applications
Servers
Storage
JBOD
Networking
Output Features
6 Low-power HCSL (LP-HCSL) output pairs (0632E)
6 Low-power HCSL (LP-HCSL) output pairs with 85Zout
(0652E)
Features
SMBus write lock feature; increases system security
LP-HCSL outputs; eliminate 12 resistors, save 20mm2 of area
(0632E)
LP-HCSL outputs with 85Zout; eliminate 24 resistors, save
48mm2 of area (0652E)
6 OE# pins; hardware control of each output
Selectable PLL BW; minimizes jitter peaking in cascaded PLL
topologies
Hardware/SMBus control of PLL bandwidth and bypass;
change mode without power cycle
Spread spectrum compatible; tracks spreading input clock for
EMI reduction
100MHz PLL mode; UPI support
5 × 5 mm 40-QFN package; small board footprint
Key Specifications
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
Input-to-output delay: Fixed at 0ps
Input-to-output delay variation < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: QPI/UPI > 9.6GB/s < 0.2ps rms
Phase jitter: IF-UPI < 1.0ps rms
Block Diagram
VDDR
VDDA
VDD x9
DIFIN#
DIFIN
PLL
FBOUT_NC#
FBOUT_NC
DIF5#
DIF5
vSMB_WRTLOCK
SMBCLK
SMBDAT
SMBus Factory
Engine Configuration
6 outputs
^vHIBW_BYPM-LOBW#
^CKPWRGD_PD#
vOE[5:0]#
Control Logic
Resistors are integrated on 9ZXL065x
devices and external on 9ZXL063x devices
GNDR
EPAD/GND
DIF0#
DIF0
©2018 Integrated Device Technology, Inc.
1
November 30, 2018

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