9ZXL0851E Datasheet | 8-Output DB800ZL





9ZXL0851E PDF File (Datasheet) Download

Part Number 9ZXL0851E
Description 8-Output DB800ZL
Manufacture IDT
Total Page 18 Pages
PDF Download Download 9ZXL0851E PDF File

Features: 8-Output DB800ZL for PCIe Gen1–4 and Q PI/UPI 9ZXL0831E / 9ZXL0851E Datasheet Description The 9ZXL0831E / 9ZXL0851E are second-generation enhanced perform ance DB800ZL differential buffers. The parts are pin-compatible upgrades to th e 9ZXL0831A and 9ZXL0851A, while offeri ng a much improved phase jitter perform ance. A fixed external feedback maintai ns low drift for critical QPI/UPI appli cations. PCIe Clocking Architectures Su pported ▪ Common Clocked (CC) ▪ Ind ependent Reference (IR) with and withou t spread spectrum Typical Application Servers ▪ Storage ▪ Networking SSDs Output Features ▪ 8 Low-Power (LP) HCSL output pairs (0831E) ▪ 8 L ow-Power (LP) HCSL output pairs with 85 Ω Zout (0851E) Features ▪ LP-HCSL outputs; eliminate 16 resistors, save 2 7mm2 of area (0831E) ▪ LP-HCSL output s with 85Ω Zout; eliminate 32 resisto rs, save 64mm2 of area (0851E) ▪ 8 OE # pins; hardware control of each output ▪ Selectable PLL BW; minimizes jitter peaking in cascaded PL.

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8-Output DB800ZL for PCIe
Gen1–4 and QPI/UPI
9ZXL0831E / 9ZXL0851E
Datasheet
Description
The 9ZXL0831E / 9ZXL0851E are second-generation enhanced
performance DB800ZL differential buffers. The parts are
pin-compatible upgrades to the 9ZXL0831A and 9ZXL0851A, while
offering a much improved phase jitter performance. A fixed external
feedback maintains low drift for critical QPI/UPI applications.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Typical Application
Servers
Storage
Networking
SSDs
Output Features
8 Low-Power (LP) HCSL output pairs (0831E)
8 Low-Power (LP) HCSL output pairs with 85Zout (0851E)
Features
LP-HCSL outputs; eliminate 16 resistors, save 27mm2 of area
(0831E)
LP-HCSL outputs with 85Zout; eliminate 32 resistors, save
64mm2 of area (0851E)
8 OE# pins; hardware control of each output
Selectable PLL BW; minimizes jitter peaking in cascaded PLL
topologies
Hardware/SMBus control of PLL bandwidth and bypass; change
mode without power cycle
Spread spectrum compatible; tracks spreading input clock for EMI
reduction
100MHz & 133.33MHz PLL mode; UPI and legacy QPI support
6 × 6 mm 48-VFQFPN package; small board footprint
Key Specifications
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50ps
Input-to-output delay: Fixed at 0ps
Input-to-output delay variation < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: QPI/UPI > 9.6GB/s < 0.2ps rms
Phase jitter: IF-UPI < 1.0ps rms
Block Diagram
VDDR
VDDA
VDD x7
DIFIN#
DIFIN
PLL
FBOUT_NC#
FBOUT_NC
DIF7#
DIF7
^100M_133M#
SMBCLK
SMBDAT
^vHIBW_BYPM-LOBW#
^CKPWRGD_PD#
vOE[7:0]#
SMBus Factory
Engine Configuration
8 outputs
Control Logic
Resistors are integrated on 9ZXL085x devices and
external on 9ZXL083x devices
GNDR
EPAD/GND
DIF0#
DIF0
©2018 Integrated Device Technology, Inc
1
November 30, 2018

                    
                    






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