9ZXL1251E Datasheet: 12-Output DB1200ZL





9ZXL1251E 12-Output DB1200ZL Datasheet

Part Number 9ZXL1251E
Description 12-Output DB1200ZL
Manufacture IDT
Total Page 21 Pages
PDF Download Download 9ZXL1251E Datasheet PDF

Features: 12-Output DB1200ZL for PCIe Gen1–4 and UPI 9ZXL1231E / 9ZXL1251E Datasheet Description The 9ZXL1231E / 9ZXL1251E a re second-generation, enhanced performa nce DB1200ZL differential buffers. The parts are pin-compatible upgrades to th e 9ZXL1231A and 9ZXL1251A, while offeri ng much improved phase jitter performan ce and increased system security featur es. A fixed external feedback maintains low drift for critical QPI/UPI applica tions. PCIe Clocking Architectures Supp orted ▪ Common Clocked (CC) ▪ Indep endent Reference (IR) with and without spread spectrum Typical Applications Servers ▪ Storage ▪ Networking SSDs Output Features ▪ 12 Low-Power (LP) HCSL output pairs (1231E) ▪ 12 Low-Power (LP) HCSL output pairs with 8 5Ω Zout (1251E) Block Diagram VDDR VDDA Features ▪ LP-HCSL outputs; el iminate 24 resistors, save 41mm2 of are a (1231E) ▪ LP-HCSL outputs with 85 Zout; eliminate 48 resistors, save 82 mm2 of area (1251E) ▪ 12 OE# pins; hardware control of each o.

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12-Output DB1200ZL for PCIe
Gen1–4 and UPI
9ZXL1231E / 9ZXL1251E
Datasheet
Description
The 9ZXL1231E / 9ZXL1251E are second-generation, enhanced
performance DB1200ZL differential buffers. The parts are
pin-compatible upgrades to the 9ZXL1231A and 9ZXL1251A,
while offering much improved phase jitter performance and
increased system security features. A fixed external feedback
maintains low drift for critical QPI/UPI applications.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Typical Applications
Servers
Storage
Networking
SSDs
Output Features
12 Low-Power (LP) HCSL output pairs (1231E)
12 Low-Power (LP) HCSL output pairs with 85Zout (1251E)
Block Diagram
VDDR
VDDA
Features
LP-HCSL outputs; eliminate 24 resistors, save 41mm2 of area
(1231E)
LP-HCSL outputs with 85Zout; eliminate 48 resistors, save
82mm2 of area (1251E)
12 OE# pins; hardware control of each output
9 selectable SMBus addresses; multiple devices can share the
same SMBus segment
Selectable PLL BW; minimizes jitter peaking in cascaded PLL
topologies
Hardware/SMBus control of PLL bandwidth and bypass;
change mode without power cycle
Spread spectrum compatible; tracks spreading input clock for
EMI reduction
100 and 133.33 MHz PLL Mode; UPI and legacy QPI support
9 x 9 mm 64-VFQFPN package; small board footprint
Key Specifications
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50ps
Input-to-output delay: fixed at 0ps
Input-to-output delay variation < 50ps
PCIe Gen4 phase jitter: < 0.5ps rms
Phase jitter: QPI/UPI > 9.6GB/s < 0.2ps rms
Phase jitter: IF-UPI < 1.0ps rms
VDD x3
VDDIO x4
DIF_IN#
DIF_IN
PLL
FBOUT_NC#
FBOUT_NC
DIF11#
DIF11
^100M_133M#
vSADR[1:0]_tri
SMBCLK
SMBDAT
SMBus Factory
Engine Configuration
12
outputs
^vHIBW_BYPM-LOBW#
^CKPWRGD_PD#
vOE[11:0]#
Control Logic
Resistors are integrated on 9ZXL125x devices and
external on 9ZXL123x devices
GNDA
GND x7
DIF0#
DIF0
©2018 Integrated Device Technology, Inc
1
November 30, 2018

                    
                    






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