9FGL0251 Datasheet: 2-Output 3.3V PCIe Clock Generator





9FGL0251 2-Output 3.3V PCIe Clock Generator Datasheet

Part Number 9FGL0251
Description 2-Output 3.3V PCIe Clock Generator
Manufacture IDT
Total Page 21 Pages
PDF Download Download 9FGL0251 Datasheet PDF

Features: 2-Output 3.3V PCIe Clock Generator 9FGL 0241 / 9FGL0251 Datasheet Description The 9FGL0241 / 9FGL0251 devices are 2-o utput clock generators in IDT's 3.3V Fu ll-Featured PCIe family. Each output ha s a dedicated OE# pin for clock managem ent. Two different spread spectrum leve ls in addition to spread off are suppor ted. The 9FGL0241 / 9FGL0251 supports P CIe Gen1–4 Common Clocked architectur es (CC) and PCIe Separate Reference no- Spread (SRnS) and Separate Reference In dependent Spread (SRIS) clocking archit ectures. Typical Applications ▪ Serve rs/High-Performance Computing/Accelerat ors ▪ Storage ▪ Embedded Systems/In dustrial Control Output Features ▪ Tw o 100MHz Low-Power HCSL (LP-HCSL) DIF o utput pairs: • 9FGL0241 default Zout = 100Ω • 9FGL0251 default Zout = 85 Ω ▪ One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support ▪ See AN-8 91 for easy AC-coupling to other logic families Key Specifications ▪ PCIe Ge n1–4 CC compliant; Gen2–3 SRIS compliant ▪ DIF cycle-to-c.

Keywords: 9FGL0251, datasheet, pdf, IDT, 2-Output, 3.3V, PCIe, Clock, Generator, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

2-Output 3.3V PCIe Clock
Generator
9FGL0241 / 9FGL0251
Datasheet
Description
The 9FGL0241 / 9FGL0251 devices are 2-output clock generators
in IDT's 3.3V Full-Featured PCIe family. Each output has a
dedicated OE# pin for clock management. Two different spread
spectrum levels in addition to spread off are supported. The
9FGL0241 / 9FGL0251 supports PCIe Gen1–4 Common Clocked
architectures (CC) and PCIe Separate Reference no-Spread
(SRnS) and Separate Reference Independent Spread (SRIS)
clocking architectures.
Typical Applications
Servers/High-Performance Computing/Accelerators
Storage
Embedded Systems/Industrial Control
Output Features
Two 100MHz Low-Power HCSL (LP-HCSL) DIF output pairs:
9FGL0241 default Zout = 100
9FGL0251 default Zout = 85
One 3.3V LVCMOS REF output with Wake-On-LAN (WOL)
support
See AN-891 for easy AC-coupling to other logic families
Key Specifications
PCIe Gen1–4 CC compliant; Gen2–3 SRIS compliant
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF 12kHz–20MHz phase jitter is < 2ps rms when SSC is off
REF phase jitter is < 300fs rms, SSC off; < 1.5ps rms, SSC on
±100ppm frequency accuracy on all clocks
Features
Direct connection to loads saves 8 resistors compared to
standard PCIe devices
112mW typical power consumption
SMBus-selectable optimization features:
Control input polarity
Control input pull-ups/pull-downs
Slew rate for each output
Differential output amplitude
33, 85or 100output impedance per output
SMBus interface not required for device operation at default
configuration
Contact factory for customized versions
25MHz input frequency
Two OE# pins
Pin-selectable SRnS, CC 0% and CC/SRIS -0.5% spread on
DIF outputs
SMBus-selectable CC/SRIS -0.25% spread
Clean switching between the CC/SRIS spread spectrum
amounts
DIF outputs blocked until PLL is locked; clean system start-up
2 selectable SMBus addresses
Space-saving 4 × 4 mm 24-VFQFPN package
Block Diagram
vOE(1:0)#
XIN/CLKIN_25
25MHz
X2
vSADR
^vSS_EN_tri
SDATA_3.3
SCLK_3.3
^CKPWRGD_PD#
VDDA
2
VDDXTAL VDDDIG
VDD x2
Control
Logic
SSC Capable
PLL
REF
DIF1#
DIF1
DIF0#
DIF0
©2018 Integrated Device Technology, Inc.
GNDA
GNDDIG GND x2 EPAD/GND GNDXTAL/GNDREF
1
September 12, 2018

                    
                    






Index : 0  1  2  3   4  5  6  7   8  9  A  B   C  D  E  F   G  H  I  J   K  L  M  N   O  P  Q  R   S  T  U  V   W  X  Y  Z
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)