9FGL0441 Datasheet: 4-Output 3.3V PCIe Clock Generator





9FGL0441 4-Output 3.3V PCIe Clock Generator Datasheet

Part Number 9FGL0441
Description 4-Output 3.3V PCIe Clock Generator
Manufacture IDT
Total Page 22 Pages
PDF Download Download 9FGL0441 Datasheet PDF

Features: 4-Output 3.3V PCIe Clock Generator 9FGL 0441 / 9FGL0451 Datasheet Description The 9FGL0441 / 9FGL0451 devices are 4-o utput clock generators in IDT's 3.3V Fu ll-Featured PCIe family. Each output ha s a dedicated OE# pin for clock managem ent. Two different spread spectrum leve ls in addition to spread off are suppor ted. The 9FGL0441 / 9FGL0451 supports P CIe Gen1–4 Common Clocked architectur es (CC) and PCIe Separate Reference no- Spread (SRnS) and Separate Reference In dependent Spread (SRIS) clocking archit ectures. Typical Applications ▪ Serve rs/High-Performance Computing/Accelerat ors ▪ Storage ▪ Embedded Systems/In dustrial Control Output Features ▪ Fo ur 100MHz Low-Power HCSL (LP-HCSL) DIF pairs: • 9FGL0441 default Zo = 100Ω • 9FGL0451 default Zo = 85Ω ▪ On e 3.3V LVCMOS REF output; Wake-On-LAN ( WOL) support ▪ See AN-891 for easy AC -coupling to other logic families Key S pecifications ▪ PCIe Gen1–4 CC comp liant; Gen2–3 SRIS compliant ▪ DIF cycle-to-cycle jitter < .

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4-Output 3.3V PCIe Clock
Generator
9FGL0441 / 9FGL0451
Datasheet
Description
The 9FGL0441 / 9FGL0451 devices are 4-output clock generators
in IDT's 3.3V Full-Featured PCIe family. Each output has a
dedicated OE# pin for clock management. Two different spread
spectrum levels in addition to spread off are supported. The
9FGL0441 / 9FGL0451 supports PCIe Gen1–4 Common Clocked
architectures (CC) and PCIe Separate Reference no-Spread
(SRnS) and Separate Reference Independent Spread (SRIS)
clocking architectures.
Typical Applications
Servers/High-Performance Computing/Accelerators
Storage
Embedded Systems/Industrial Control
Output Features
Four 100MHz Low-Power HCSL (LP-HCSL) DIF pairs:
9FGL0441 default Zo = 100
9FGL0451 default Zo = 85
One 3.3V LVCMOS REF output; Wake-On-LAN (WOL) support
See AN-891 for easy AC-coupling to other logic families
Key Specifications
PCIe Gen1–4 CC compliant; Gen2–3 SRIS compliant
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF 12kHz–20MHz phase jitter is < 2ps rms when SSC is off
REF phase jitter < 300fs rms; SSC off and < 1.5ps rms; SSC on
±100ppm frequency accuracy on all clocks
Features
Direct connection to loads saves 16 resistors compared to
standard PCIe devices
142mW typical power consumption
SMBus-selectable optimization features:
Control input polarity
Control input pull-up/pull-down
Slew rate for each output
Differential output amplitude
33, 85or 100output impedance for each output
SMBus interface not required for device operation at default
configuration
Contact factory for customized versions
25MHz input frequency
4 OE# pins
Pin-selectable SRnS, CC 0% and CC/SRIS -0.5% spread on
DIF outputs
SMBus-selectable CC/SRIS -0.25% spread
Clean switching between the CC/SRIS spread spectrum
amounts
DIF outputs blocked until PLL is locked; clean system start-up
2 selectable SMBus addresses
Space-saving 5 × 5 mm 32-VFQFPN package
Block Diagram
vOE(3:0)#
XIN/CLKIN_25
25MHz
X2
vSADR
^vSS_EN_tri
SDATA_3.3
SCLK_3.3
^CKPWRGD_PD#
VDDA
4
VDDREF, VDDXTAL VDDDIG
VDDO x2
REF
Control
Logic
SSC Capable
PLL
DIF3#
DIF3
DIF2#
DIF2
DIF1#
DIF1
DIF0#
DIF0
©2018 Integrated Device Technology, Inc.
GNDA
GNDDIG GND x3 EPAD/GND GNDXTAL, GNDREF
1
September 18, 2018

                    
                    






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