9FGL0641 Datasheet | 6-Output 3.3V PCIe Clock Generator





(Datasheet) 9FGL0641 Datasheet PDF Download

Part Number 9FGL0641
Description 6-Output 3.3V PCIe Clock Generator
Manufacture IDT
Total Page 22 Pages
PDF Download Download 9FGL0641 Datasheet PDF

Features: 6-Output 3.3V PCIe Clock Generator 9FGL 0641 / 9FGL0651 Datasheet Description The 9FGL0641 / 9FGL0651 devices are 3.3 V members of IDT's 3.3V Full-Featured P CIe family. The devices have 6 output e nables for clock management and support 2 different spread spectrum levels in addition to spread off. The 9FGL0641 / 9FGL0651 supports PCIe Gen1–4 Common Clocked architectures (CC), PCIe Separa te Reference no-Spread (SRnS) and Separ ate Reference Independent Spread (SRIS) clocking architectures. Typical Applic ations ▪ Servers/High-Performance Com puting/Accelerators ▪ Storage ▪ Emb edded Systems/Industrial Control Output Features ▪ Six 100MHz Low-Power HCSL (LP-HCSL) DIF pairs: • 9FGL0641 defa ult Zo = 100Ω • 9FGL0651 default Zo = 85Ω ▪ One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support ▪ See AN-891 for easy AC-coupling to other l ogic families Key Specifications ▪ PC Ie Gen1–4 CC compliant; Gen2–3 SRIS compliant ▪ DIF cycle-to-cycle jitter < 50ps ▪ DIF output-.

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6-Output 3.3V PCIe Clock
Generator
9FGL0641 / 9FGL0651
Datasheet
Description
The 9FGL0641 / 9FGL0651 devices are 3.3V members of IDT's
3.3V Full-Featured PCIe family. The devices have 6 output
enables for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL0641 /
9FGL0651 supports PCIe Gen1–4 Common Clocked architectures
(CC), PCIe Separate Reference no-Spread (SRnS) and Separate
Reference Independent Spread (SRIS) clocking architectures.
Typical Applications
Servers/High-Performance Computing/Accelerators
Storage
Embedded Systems/Industrial Control
Output Features
Six 100MHz Low-Power HCSL (LP-HCSL) DIF pairs:
9FGL0641 default Zo = 100
9FGL0651 default Zo = 85
One 3.3V LVCMOS REF output with Wake-On-LAN (WOL)
support
See AN-891 for easy AC-coupling to other logic families
Key Specifications
PCIe Gen1–4 CC compliant; Gen2–3 SRIS compliant
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF 12kHz–20MHz phase jitter is < 2ps rms when SSC is off
REF phase jitter is < 150fs rms; SSC off
±100ppm frequency accuracy on all clocks
Features
Direct connection to loads saves 24 resistors compared to
standard PCIe devices
188mW typical power consumption at 3.3V
VDDIO rail allows 30% power savings at optional 1.05V
SMBus-selectable features allows optimization to customer
requirements:
Control input polarity
Control input pull-up/pull-down
Slew rate for each output
Differential output amplitude
33, 85or 100output impedance for each output
Devices contain default configuration; SMBus not required
Contact factory for customized versions
25MHz input frequency
OE# pins; support DIF power management
Pin-selectable SRnS, CC 0% and CC/SRIS -0.5% spread
SMBus-selectable CC/SRIS -0.25% spread
Clean switching between the CC/SRIS spread settings
DIF outputs blocked until PLL is locked; clean system start-up
2 selectable SMBus addresses
Space saving 5 × 5 mm 40-VFQFPN package
Block Diagram
vOE(5:0)#
XIN/CLKIN_25
VDDA VDDREF, VDDXTAL VDDDIG
6
VDDIOx5
REF
25MHz
X2
vSADR
^vSS_EN_tri
SDATA_3.3
SCLK_3.3
^CKPWRGD_PD#
SSC Capable
PLL
Control
Logic
DIF5#
DIF5
DIF4#
DIF4
DIF3#
DIF3
DIF2#
DIF2
DIF1#
DIF1
DIF0#
DIF0
©2018 Integrated Device Technology, Inc.
GNDDIG
1
EPAD/GND
September 18, 2018

                    
                    






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