9FGL0851 Datasheet: 8-Output 3.3V PCIe Clock Generator





9FGL0851 8-Output 3.3V PCIe Clock Generator Datasheet

Part Number 9FGL0851
Description 8-Output 3.3V PCIe Clock Generator
Manufacture IDT
Total Page 22 Pages
PDF Download Download 9FGL0851 Datasheet PDF

Features: 8-Output 3.3V PCIe Clock Generator 9FGL 0841 / 9FGL0851 Datasheet Description The 9FGL0841 / 9FGL0851 devices are 8-o utput clock generators in IDT's 3.3V Fu ll-Featured PCIe family. Each output ha s a dedicated OE# pin for clock managem ent.Two different spread spectrum level s in addition to spread off are support ed. The 9FGL0841 / 9FGL0851 supports PC Ie Gen1–4 Common Clocked architecture s (CC) and PCIe Separate Reference no-S pread (SRnS) and Separate Reference Ind ependent Spread (SRIS) clocking archite ctures. Typical Applications ▪ Server s/High-Performance Computing/Accelerato rs ▪ Storage ▪ Embedded systems/Ind ustrial control Output Features ▪ 8 1 00MHz Low-Power HCSL (LP-HCSL) DIF pair s: • 9FGL0841 default Zo = 100Ω • 9FGL0851 default Zo = 85Ω ▪ 1 3.3V LVCMOS REF output; Wake-On-LAN (WOL) s upport ▪ See AN-891 for easy AC-coupl ing to other logic families Key Specifi cations ▪ PCIe Gen1–4 CC compliant; Gen2–3 SRIS compliant ▪ DIF cycle-to-cycle jitter < 50ps .

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8-Output 3.3V PCIe Clock
Generator
9FGL0841 / 9FGL0851
Datasheet
Description
The 9FGL0841 / 9FGL0851 devices are 8-output clock generators
in IDT's 3.3V Full-Featured PCIe family. Each output has a
dedicated OE# pin for clock management.Two different spread
spectrum levels in addition to spread off are supported. The
9FGL0841 / 9FGL0851 supports PCIe Gen1–4 Common Clocked
architectures (CC) and PCIe Separate Reference no-Spread
(SRnS) and Separate Reference Independent Spread (SRIS)
clocking architectures.
Typical Applications
Servers/High-Performance Computing/Accelerators
Storage
Embedded systems/Industrial control
Output Features
8 100MHz Low-Power HCSL (LP-HCSL) DIF pairs:
9FGL0841 default Zo = 100
9FGL0851 default Zo = 85
1 3.3V LVCMOS REF output; Wake-On-LAN (WOL) support
See AN-891 for easy AC-coupling to other logic families
Key Specifications
PCIe Gen1–4 CC compliant; Gen2–3 SRIS compliant
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF 12kHz–20MHz phase jitter is < 2ps rms when SSC is off
REF phase jitter < 300fs rms; SSC off and < 1.9ps rms; SSC on
±100ppm frequency accuracy on all clocks
Features
Direct connection to loads saves 32 resistors compared to
standard PCIe devices
206mW typical power consumption (at 3.3V); eliminates
thermal concerns
VDDIO rail allows 35% power savings at optional 1.05V;
maximum power savings
SMBus-selectable features allows optimization to customer
requirements:
Control input polarity
Control input pull-ups/pull-downs
Slew rate for each output
Differential output amplitude
33, 85or 100output impedance for each output
Devices contain default configuration; SMBus not required
Contact factory for customized versions
25MHz input frequency
OE# pins; support DIF power management
Pin-selectable SRnS, CC 0% and CC/SRIS -0.5% spread
SMBus-selectable CC/SRIS -0.25% spread
Clean switching between the CC/SRIS spread settings
DIF outputs blocked until PLL is locked; clean system start-up
2 selectable SMBus addresses
Space saving 6 × 6 mm 48-VFQFPN package
Block Diagram
vOE(7:0)#
XIN/CLKIN_25
25MHz
X2
vSADR
^vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
VDDA VDDREF / VDDXTAL VDDDIG VDDOx2 / /VDDIOx5
8
SSC Capable
PLL
Control
Logic
REF
DIF7#
DIF7
DIF6#
DIF6
DIF5#
DIF5
DIF4#
DIF4
DIF3#
DIF3
DIF2#
DIF2
DIF1#
DIF1
DIF0#
DIF0
GNDXTAL / GNDREF GNDDIG GNDx2 EPAD
©2018 Integrated Device Technology, Inc.
1
September 17, 2018

                    
                    






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