9FGV1006B Data Sheet PDF | IDT





(Datasheet) 9FGV1006B PDF Download

Part Number 9FGV1006B
Description Low-Power Programmable PhiClock Generator
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9FGV1006B Datasheet PDF

Features: Low Phase-Noise, Low-Power Programmable PhiClock™ Generator 9FGV1006B Datash eet Description The 9FGV1006B is a mem ber of IDT's PhiClock™ programmable c lock generator family. The 9FGV1006B pr ovides two copies of a single integer, fractional or spread spectrum output fr equency and one copy of the crystal ref erence input. Two select pins allow for hardware selection of the desired conf iguration, or two I2C bits allow easy s oftware selection of the desired config uration. The user may configure any one of the four OTP configurations as the default when operating in I2C mode. Fou r unique I2C addresses are available, a llowing easy I2C access to multiple com ponents. Typical Applications ▪ HPC Storage ▪ 10G/25G/100G Ethernet Fiber Optic Modules ▪ eSSDs ▪ NVL ink Output Features ▪ 2 programmable output pairs plus 1 LVCMOS REF output 1 integer, fractional or spread spec trum output frequency per configuration ▪ 10MHz–325MHz LVDS or LP-HCSL outputs ▪ 10MHz–200MHz .

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9FGV1006B datasheet
Low Phase-Noise, Low-Power
Programmable PhiClock™ Generator
9FGV1006B
Datasheet
Description
The 9FGV1006B is a member of IDT's PhiClock™ programmable
clock generator family. The 9FGV1006B provides two copies of a
single integer, fractional or spread spectrum output frequency and
one copy of the crystal reference input. Two select pins allow for
hardware selection of the desired configuration, or two I2C bits
allow easy software selection of the desired configuration. The
user may configure any one of the four OTP configurations as the
default when operating in I2C mode. Four unique I2C addresses
are available, allowing easy I2C access to multiple components.
Typical Applications
HPC
Storage
10G/25G/100G Ethernet
Fiber Optic Modules
eSSDs
NVLink
Output Features
2 programmable output pairs plus 1 LVCMOS REF output
1 integer, fractional or spread spectrum output frequency per
configuration
10MHz–325MHz LVDS or LP-HCSL outputs
10MHz–200MHz LVCMOS outputs
Features
1.8V to 3.3V power supplies
Individual 1.8V to 3.3V VDDO for each output pair
Supports HCSL, LVDS and LVCMOS I/O standards
Supports LVPECL and CML logic with easy AC coupling – see
application note AN-891 for alternate terminations
HCSL utilizes IDT's LP-HCSL technology for improved
performance, lower power and higher integration:
Programmable output impedance of 85or 100
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I2C
Internal crystal load capacitors
< 100mW at 1.8V with LP-HCSL outputs at 100MHz (LP-HCSL)
4 programmable I2C addresses: D0, D2, D4, D6
Supported by IDT Timing Commander™ software and Web
Configuration tool
3 × 3 mm 16-LGA with integrated crystal option (9FGV1006BQ)
Programmable spread spectrum modulation frequency and
amount
Key Specifications
276fs rms typical phase jitter at 156.25MHz (12kHz–20MHz)
< 0.2ps rms PCIe Gen4 Common Clocked jitter at 100MHz
PCIe Clocking Architectures
PCIe Gen1–4 Common Clocked (CC)
Independent Reference without spread spectrum (SRnS)
Independent Reference with spread spectrum (SRIS)
Block Diagram
VDDDp OTP_VPP VDDAp VDDO0
XIN/CLKIN
XO
Crystal is
integrated on
9FGV1006Q
vSEL_I2C#
^SEL0/SCL
^SEL1/SDA
OSC
Fractional
PLL
(SSC)
INT
DIV
SMBus
Factory
Engine Configuration
REF0
VDDREFp
OUT1#
OUT1
VDDO1
OUT0#
OUT0
VDDO0
Control Logic
Internal terminations are available when LP-HCSL output format is selected.
©2018 Integrated Device Technology, Inc.
EPAD/GND
1
August 28, 2018

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