9DBL0242 Datasheet: 2-output 3.3V PCIe Zero-Delay Buffer





9DBL0242 2-output 3.3V PCIe Zero-Delay Buffer Datasheet

Part Number 9DBL0242
Description 2-output 3.3V PCIe Zero-Delay Buffer
Manufacture IDT
Total Page 19 Pages
PDF Download Download 9DBL0242 Datasheet PDF

Features: 2-output 3.3V PCIe Zero-Delay Buffer 9D BL0242 / 9DBL0252 DATASHEET Descripti on The 9DBL0242 / 9DBL0252 devices are 3.3V members of IDT's Full-Featured PCI e family. The devices support PCIe Gen1 -4 Common Clocked (CC) and PCIe Gen2 Se parate Reference Independent Spread (SR IS) systems. It offers a choice of inte grated output terminations providing di rect connection to 85 or 100 tran smission lines. The 9DBL02P2 can be fac tory programmed with a user-defined pow er up default SMBus configuration. Reco mmended Application PCIe Gen1-4 clock d istribution for Riser Cards, Storage, N etworking, JBOD, Communications, Access Points Output Features • 2 – 1-200 MHz Low-Power (LP) HCSL DIF pairs • 9DBL0242 default ZOUT = 100 • 9DBL 0252 default ZOUT = 85 • 9DBL02P2 factory programmable defaults • Easy AC-coupling to other logic families, se e IDT application note AN-891 Key Speci fications • PCIe Gen1-2-3-4 CC compli ant in ZDB mode • PCIe Gen2 SRIS compliant in ZDB mode • Su.

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2-output 3.3V PCIe Zero-Delay
Buffer
9DBL0242 / 9DBL0252
DATASHEET
Description
The 9DBL0242 / 9DBL0252 devices are 3.3V members of
IDT's Full-Featured PCIe family. The devices support PCIe
Gen1-4 Common Clocked (CC) and PCIe Gen2 Separate
Reference Independent Spread (SRIS) systems. It offers a
choice of integrated output terminations providing direct
connection to 85or 100transmission lines. The
9DBL02P2 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
2 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0242 default ZOUT = 100
9DBL0252 default ZOUT = 85
9DBL02P2 factory programmable defaults
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC compliant in ZDB mode
PCIe Gen2 SRIS compliant in ZDB mode
Supports PCIe Gen2-3 SRIS in fan-out mode
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Features/Benefits
Direct connection to 100(xx42) or 85(xx52)
transmission lines; saves 8 resistors compared to standard
PCIe devices
100mW typical power consumption in PLL mode; minimal
power consumption
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
– slew rate for each output
– differential output amplitude
– output impedance for each output
– 50, 100, 125MHz operating frequency
Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
Note: Resistors default to internal on xx42/xx52 devices. P2 devices have programmable default impedances on an output-by-output basis.
9DBL0242 / 9DBL0252 FEBRUARY 8, 2017
1
©2017 Integrated Device Technology, Inc.

                    
                    






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