9DBL0841 Datasheet: 8-output 3.3V PCIe Zero-Delay Buffer





9DBL0841 8-output 3.3V PCIe Zero-Delay Buffer Datasheet

Part Number 9DBL0841
Description 8-output 3.3V PCIe Zero-Delay Buffer
Manufacture IDT
Total Page 19 Pages
PDF Download Download 9DBL0841 Datasheet PDF

Features: 8-output 3.3V PCIe Zero-Delay Buffer 9D BL0841 / 9DBL0851 Description The 9DBL 0841 / 9DBL0851 devices are 3.3V member s of IDT's Full-Featured PCIe family. T he 9DBL0841 / 9DBL0851 supports PCIe Ge n1-4 Common Clocked (CC) and PCIe Separ ate Reference Independent Spread (SRIS) systems. It offers a choice of integra ted output terminations providing direc t connection to 85Ω or 100Ω transmi ssion lines. The 9DBL08P1 can be factor y programmed with a user-defined power up default SMBus configuration. Recomme nded Application PCIe Gen1-4 clock dist ribution for Riser Cards, Storage, Netw orking, JBOD, Communications, Access Po ints Output Features • 8 – 1-200 MH z Low-Power (LP) HCSL DIF pairs • 9DB L0841 default ZOUT = 100 • 9DBL085 1 default ZOUT = 85 • 9DBL08P1 fac tory programmable defaults • Easy AC- coupling to other logic families, see I DT application note AN-891 Key Specific ations • PCIe Gen1-2-3-4 CC compliant in ZDB mode • PCIe Gen2 SRIS compliant in ZDB mode • Suppo.

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8-output 3.3V PCIe Zero-Delay
Buffer
9DBL0841 / 9DBL0851
Description
The 9DBL0841 / 9DBL0851 devices are 3.3V members of
IDT's Full-Featured PCIe family. The 9DBL0841 / 9DBL0851
supports PCIe Gen1-4 Common Clocked (CC) and PCIe
Separate Reference Independent Spread (SRIS) systems. It
offers a choice of integrated output terminations providing
direct connection to 85or 100transmission lines. The
9DBL08P1 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0841 default ZOUT = 100
9DBL0851 default ZOUT = 85
9DBL08P1 factory programmable defaults
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC compliant in ZDB mode
PCIe Gen2 SRIS compliant in ZDB mode
Supports PCIe Gen2-3 SRIS in fan-out mode
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Block Diagram
DATASHEET
Features/Benefits
Direct connection to 100(0841) or 85(0851)
transmission lines; saves 32 resistors compared to
standard PCIe devices
211mW typical power consumption (PLL mode@3.3V);
eliminates thermal concerns
VDDIO allows 35% power savings at optional 1.05V;
maximum power savings
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
slew rate for each output
differential output amplitude
output impedance for each output
50, 100, 125MHz operating frequency
Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF3.3
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DBL0841 / 9DBL0851 FEBRUARY 9, 2017
1
©2017 Integrated Device Technology, Inc.

                    
                    






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