9DBL09P1 Data Sheet PDF | IDT





(Datasheet) 9DBL09P1 PDF Download

Part Number 9DBL09P1
Description 9-Output 3.3V PCIe Fanout Buffer
Manufacture IDT
Total Page 19 Pages
PDF Download Download 9DBL09P1 Datasheet PDF

Features: 9-Output 3.3V PCIe Fanout Buffer 9DBL09 x1 Description The 9DBL09x1 devices ar e 3.3V members of IDT's Full-Featured P CIe clock family. The 9DBL09x1 devices support PCIe Gen1–4 Common Clocked (C C) and PCIe Separate Reference Independ ent Spread (SRIS) systems. They offer a choice of integrated output terminatio ns providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL 09P1 can be factory programmed with a u ser-defined power up default SMBus conf iguration. Recommended Application PCIe Gen1–4 clock distribution for Riser Cards, Storage, Networking, JBOD, Commu nications, Access Points Output Feature s • 9 – 1-200 MHz Low-Power (LP) HC SL DIF pairs • 9DBL0941 default Zout = 100Ω • 9DBL0951 default Zout = 85 Ω • 9DBL09P1 factory programmable d efaults • Easy AC-coupling to other l ogic families, see IDT application note AN-891. Key Specifications • DIF add itive cycle-to-cycle jitter < 5ps • D IF output-to-output skew < 50ps • Additive phase jitter is 0p.

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9DBL09P1 datasheet
9-Output 3.3V PCIe Fanout Buffer
9DBL09x1
Description
The 9DBL09x1 devices are 3.3V members of IDT's
Full-Featured PCIe clock family. The 9DBL09x1 devices
support PCIe Gen1–4 Common Clocked (CC) and PCIe
Separate Reference Independent Spread (SRIS) systems.
They offer a choice of integrated output terminations
providing direct connection to 85or 100transmission
lines. The 9DBL09P1 can be factory programmed with a
user-defined power up default SMBus configuration.
Recommended Application
PCIe Gen1–4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
9 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0941 default Zout = 100
9DBL0951 default Zout = 85
9DBL09P1 factory programmable defaults
Easy AC-coupling to other logic families, see IDT
application note AN-891.
Key Specifications
DIF additive cycle-to-cycle jitter < 5ps
DIF output-to-output skew < 50ps
Additive phase jitter is 0ps (typical rms) for PCIe Gen1–4
CC, SRIS
Additive phase jitter 111fs rms typical at 156.25M (1.5M to
10M)
Block Diagram
vOE(8 :0)#
9
CLK_IN
CLK_IN#
v SAD R
^CKPW RGD_P D#
SDA TA_ 3. 3
SCLK_3.3
DATASHEET
Features/Benefits
Direct connection to 100(xx41) or 85(xx51)
transmission lines; saves 36 resistors compared to
standard PCIe devices
165mW typical power consumption (at 3.3V); eliminates
thermal concerns
VDDIO allows 50% power savings at optional 1.05V;
maximum power savings
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
– slew rate for each output
– differential output amplitude
– output impedance for each output
Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL differential input; can be driven by common clock
sources
Spread spectrum tolerant; allows reduction of EMI
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 48-pin 6 x 6mm VFQFPN; minimal board
space
D IF8
D IF7
D IF6
D IF5
D IF4
D IF3
D IF2
D IF1
D IF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DBL09x1 AUGUST 1, 2017
1 ©2017 Integrated Device Technology, Inc.

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