ICS87004I

1:4, Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator ICS87004I DATA SHEET General Description The ICS87004I is a highly versatile 1:4 DifferentialICS to-LVCMOS/LVTTL Clock Generator. The ICS87004I HiPerClockS™ has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. Internal bias on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL. The ICS87004I has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purp...