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3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO™
262,144 x 9
IDT72V2101
524,288 x 9
IDT72V2111
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
• Choose among the following memory organizations: IDT72V2101 ⎯ 262,144 x 9 IDT72V2111 ⎯ 524,288 x 9
• Pin-compatible with the IDT72V261/72V271 and the IDT72V281/ 72V291 SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time) • Fixed, low first word data latency time • 5V input tolerant • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Retransmit operation with fixed, low first word data latency time • Empty, Full and Half-Full flags signal FIFO status • Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets • Program partial flags by either serial or parallel means • Select IDT Standard timing (using EFand FFflags) o.