IDT71V2546XS

128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs IDT71V2546S/XS Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRITE) control pin ◆ Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ◆ 4-word burst capability (interleaved or linear) ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ Three chip enables for simple depth expansion ◆ 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ) ◆ Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP) and 119 ball grid array (BGA) Description The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM. It is designed to eliminate dead bus cycles when turning t...