SPP8525

SPP8525 P-Channel Enhancement Mode MOSFET DESCRIPTION The SPP8525 is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density , DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits, and low in-line power loss are needed in a very small outline surface mount package. FEATURES  -20V/-7.2 A,RDS(ON)=40mΩ@VGS=-4.5V  -20V/-5.2 A,RDS(ON)=52mΩ@VGS=-2.5V  -20V/-3.6 A,RDS(ON)=70mΩ@VGS=-1.8V  Super high density cell design for extremely low RDS (ON)  Exceptional on-resistance and maximum DC current capability  PPAK3x2-8L package design APPLICATIONS  Power Management in Note book  Portable Equipment  Battery Powered System  DC/DC Converter  Load Switch  DSC  LCD Display inverter PIN CONFIGURATION (PPAK3x2–8L ) PART MARKING 2020/1/21 Ver 2 Page 1 SPP8525 P-Channel Enhancement Mode MOSFET PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 Symbol D D D G S D D D Description Drain Drain Drain Gate Source Drain Drain Drain ORDERING INFORMATION Part Number Package SPP8525DN8RGB PPAK3x2–8L ※ SPP8525DN8RGB : 13” Tape Reel ; Pb – Free ; Halogen - Free ABSOULTE MAXIMUM RATINGS (TA=25℃ Unless otherwise noted) Parameter Drain-Source Voltage Gate –Source Voltage Continuous Drain Current(TJ=150℃) Pulsed Drain Current TA=25℃ TA...