Clock Buffer. 551S Datasheet

551S Buffer. Datasheet pdf. Equivalent

Part 551S
Description Low Skew 1 to 4 Clock Buffer
Feature Low Skew 1 to 4 Clock Buffer 551S DATASHEET Description The 551S is a low cost, high-speed single.
Manufacture IDT
Datasheet
Download 551S Datasheet



551S
Low Skew 1 to 4 Clock Buffer
551S
DATASHEET
Description
The 551S is a low cost, high-speed single input to four output
clock buffer. The 551S has best in class Additive Phase Jitter
of sub 50fsec.
IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize clocks.
Contact IDT for all of your clocking needs.
Features
Low additive phase jitter RMS: 50fs
Extremely low skew outputs (50ps)
Low cost clock buffer
Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
Input/Output clock frequency up to 200MHz
Non-inverting output clock
Ideal for networking clocks
Operating Voltages: 1.8V to 3.3V
Output Enable mode tri-states outputs
Advanced, low power CMOS process
Extended temperature range (-40°C to +105°C)
Block Diagram
ICLK
Q1
Q2
Q3
Q4
Output Enable
551S SEPTEMBER 20, 2018
1 ©2018 Integrated Device Technology, Inc.



551S
551S DATASHEET
Pin Assignment
ICLK
Q1
Q2
Q3
1
2
3
4
8 OE
7 VDD
6 GND
5 Q4
8 Pin (150 mil) SOIC
ICLK
Q1
Q2
Q3
1
2
3
4
8 OE
7 VDD
6 GND
5 Q4
8-pin DFN
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
Q1
Q2
Q3
Q4
GND
VDD
OE
Pin
Type
Input
Output
Output
Output
Output
Power
Power
Input
Pin Description
Clock input. Internal pull-up resistor.
Clock output 1.
Clock output 2.
Clock output 3.
Clock output 4.
Connect to ground.
Connect +1.8V, +2.5V or +3.3V.
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be
connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33series terminating resistor may
be used on each clock output if the trace is longer than 1 inch.
LOW SKEW 1 TO 4 CLOCK BUFFER
2
SEPTEMBER 20, 2018





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