Hex buffer. 74LVC07A Datasheet

74LVC07A buffer. Datasheet pdf. Equivalent

Part 74LVC07A
Description Hex buffer
Feature 74LVC07A Hex buffer with open-drain outputs Rev. 6 — 14 December 2018 Product data sheet 1. Genera.
Manufacture nexperia
Datasheet
Download 74LVC07A Datasheet



74LVC07A
74LVC07A
Hex buffer with open-drain outputs
Rev. 6 — 14 December 2018
Product data sheet
1. General description
The 74LVC07A provides six non-inverting buffers. The outputs are open-drain and can be
connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH
wired-AND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC07AD
-40 °C to +125 °C
74LVC07APW
-40 °C to +125 °C
74LVC07ABQ
-40 °C to +125 °C
Name
SO14
TSSOP14
DHVQFN14
Description
Version
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
plastic thin small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal
SOT762-1
enhanced very thin quad flat package;
no leads; 14 terminals; body 2.5 x 3 x 0.85 mm



74LVC07A
Nexperia
4. Functional diagram
74LVC07A
Hex buffer with open-drain outputs
1 1A
1Y 2
3 2A
2Y 4
5 3A
3Y 6
9 4A
4Y 8
11 5A
5Y 10
13 6A
6Y 12
mna535
Fig. 1. Logic symbol
1A 1
1 2 1Y
2A 3
1 4 2Y
3A 5
1 6 3Y
4A 9
1 8 4Y
11
5A
1
10 5Y
13
6A
1
12 6Y
mna534
Fig. 2. IEC logic symbol
5. Pinning information
Y
A
GND
mna533
Fig. 3. Logic diagram for one gate
5.1. Pinning
74LVC07A
1A 1
14 VCC
1Y 2
13 6A
2A 3
12 6Y
2Y 4
11 5A
3A 5
10 5Y
3Y 6
9 4A
GND 7
8 4Y
001aad066
Fig. 4. Pin configuration for SO14 and TSSOP14
74LVC07A
terminal 1
index area
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND(1)
13 6A
12 6Y
11 5A
10 5Y
9 4A
001aad067
Transparent top view
(1) This is not a supply pin. The substrate is attached
to this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder this
pad.However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig. 5. Pin configuration for DHVQFN14
74LVC07A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 14 December 2018
© Nexperia B.V. 2018. All rights reserved
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