DAA CHIPSET. Si3052 Datasheet

Si3052 CHIPSET. Datasheet pdf. Equivalent

Part Si3052
Description GLOBAL PCI DAA CHIPSET
Feature GLOBAL PCI DAA CHIPSET Si3052 Si3017/11/18 Features ! Si3052 PCI DAA and Si3018 ! Watchdog timer.
Manufacture Silicon Laboratories
Datasheet
Download Si3052 Datasheet



Si3052
GLOBAL PCI DAA CHIPSET
Si3052
Si3017/11/18
Features
! Si3052 PCI DAA and Si3018
! Watchdog timer
global, Si3011 TBR21, or Si3017 ! External EPROM interface
FCC line-side DAA
! Compliant with FCC, TBR21,
! 32-bit, 33 MHz, PCI 2.3 compliant JATE, and other PTTs
interface
! 80 dB dynamic range TX/RX Path
! PPMI 1.1 and wake support with ! 2- to 4-wire Hybrid
PME and Vaux
! Patented ISOcap™ technology
! Bus master and target operation, ! >5000 V isolation
DMA controller
! Wake-on-ring and ring validation
! 16 x 8 FIFO on DMA paths
! 3.3 V digital power supply
! Interrupt controller
! 64-Pin TQFP, 0 to 70 °C
! Lowest cost external bill-of-
material (BOM)
Applications
Ordering Information
See page 97.
Pin Assignments
! V.92 soft data/fax modems
Description
The Si3052 is a system-side silicon direct access arrangement (DAA)
device that integrates a 32-bit, 33 MHz PCI bus interface. The Si3052 is
paired with the Si3018 global line-side device, Si3011 FCC/TBR21 line-
side device, or Si3017 FCC line-side device. The PCI DAA chipset is
compliant with global standards and includes a V.92 quality codec (80 dB
SNR, –75 dB THD), dc termination (50 , current limiting), ac termination
(600 , complex impedance), and an integrated hybrid.
Functional Block Diagram
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
Si30526 43
7 42
8
9
64-Lead TQFP
41
40
(epad)10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PCI
Addr/Data
PCI
Control
PCI
Interface
with
FIFOs
AOUT
DAA Control
DMA Control
Call Progress
Speaker
Si3018
DAA
Interrupt Control
ID/ROM Interface
EPROM
TIP
RING
QE
DCT
RX
IB
C1B
C2B
VREG
RNG1
Si3017/11/18
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
DCT2
IGND
DCT3
QB
QE2
SC
VREG2
RNG2
VD Vaux
GND
US Patent # 5,870,046
US Patent # 6,061,009
Patents pending
Rev. 1.0 7/03
Copyright © 2003 by Silicon Laboratories
Si3052-DS10



Si3052
Si3052/17/11/18
2 Rev. 1.0





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