SILICON DAA. Si3054 Datasheet

Si3054 DAA. Datasheet pdf. Equivalent

Part Si3054
Description GLOBAL DUAL MODE HD AUDIO/AC97 SILICON DAA
Feature Si3054/Si3018 SYSTEM-SIDE REV E OR LATER GLOBAL DUAL MODE HD AUDIO/AC’97 SILICON DAA Features Inte.
Manufacture Silicon Laboratories
Datasheet
Download Si3054 Datasheet



Si3054
Si3054/Si3018
SYSTEM-SIDE REV E OR LATER
GLOBAL DUAL MODE HD AUDIO/AC’97 SILICON DAA
Features
Intel® HD Audio and AC’97 2.3
compliant with patented serial bus
autodetection
Global phone line interface
Compliant with FCC, TBR21,
JATE, and other PTTs
80 dB dynamic range TX/RX paths
3.3 V digital power supply
Greater than 5000 V isolation
Caller ID support
Integrated ring detector
Integrated analog front end
2- to 4-wire hybrid
Low-power standby mode
Patented isolation technology
Wake-on-ring and ring validation
PnP EPROM interface
Available in lead-free/RoHS-
compliant packages
Applications
Ordering Information:
See page 113.
Software modems
Communications/network riser
(CNR)
Description
Mobile daughter cards (MDC)
Mini PCI cards
Audio/modem riser cards
The Si3054/18 is an integrated direct access arrangement (DAA) chipset that
provides a digital programmable line interface to meet global telephone line
requirements. Available in two 16-pin small outline packages (Si3054 digital
interface and Si3018 phone-line interface), the chipset eliminates the need for
an analog front end (AFE), isolation transformer, relays, opto-isolators, and a
2- to 4-wire hybrid. The Si3054/18 dramatically reduces the number of discrete
components and cost required to achieve compliance with global regulatory
requirements. The digital dual interface Si3054 complies with both the AC’97
2.3 and Intel®HD Audio 1.0 specifications and automatically configures itself to
support AC-link or HD Audio signalling through a patented serial bus
autodetection block.
Functional Block Diagram
Si3054
Link
Detector
RST/RESET
BCLK/BIT_CLK
SYNC
SDI/SDATA_IN
SDO/SDATA_OUT
HD Audio
Digital
Interface
AC97
Digital
Interface
Isolation
Interface
AOUT/ID1
EE_SD/GPIO_A/ID0
EE_SC/GPIO_B
Control
Interface
Si3018
Isolation
Interface
Hybrid and
DC
Termination
Ring Detect
Off-Hook
RX
SC
FILT
FILT2
DCT
DCT2
DCT3
VREG
VREG2
RNG1
RNG2
QB
QE
QE2
Pin Assignments
Si3054
(Revision E or Later)
NC1
NC2
BCLK/BIT_CLK
VD
SDI/SDATA_IN
SDO/SDATA_OUT
SYNC
RST/RESET
1
2
3
4
5
6
7
8
16 GPIO_A/EE_SC
15 GPIO_B/EE_SD/PNPID
14 NC3
13 VA
12 GND
11 AOUT
10 C1A
9 C2A
QE
DCT
RX
IB
C1B
C2B
VREG
RNG1
Si3018
1 16 DCT2
2 15 IGND
3 14 DCT3
4 13 QB
5 12 QE2
6 11 SC
7 10 VREG2
8 9 RNG2
Patent # 5,870,046
Patent # 6,061,009
Other patents pending
Rev. 1.0 1/05
Copyright © 2005 by Silicon Laboratories
Si3054/18
Downloaded from Arrow.com.



Si3054
Si3054/Si3018
2
Downloaded from Arrow.com.
Rev. 1.0





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