CRYSTAL OSCILLATOR. Si534 Datasheet

Si534 OSCILLATOR. Datasheet pdf. Equivalent

Part Si534
Description QUAD FREQUENCY CRYSTAL OSCILLATOR
Feature Si534 REVISION D QUAD FREQUENCY CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ) Features  Available .
Manufacture Silicon Laboratories
Datasheet
Download Si534 Datasheet



Si534
Si534
REVISION D
QUAD FREQUENCY CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 1.4 GHZ)
Features
Available with any-rate output
Internal fixed crystal frequency
frequencies from 10 MHz to 945 MHz ensures high reliability and low
and select frequencies to 1.4 GHz
aging
Four selectable output frequencies Available CMOS, LVPECL,
3rd generation DSPLL® with superior
jitter performance
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
3x better frequency stability than
SAW-based oscillators
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Applications
Si5602
Ordering Information:
See page 7.
SONET/SDH
Networking
SD/HD video
Description
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
The Si534 quad frequency XO utilizes Silicon Laboratories’ advanced
DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si534
is available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is
required for each output frequency, the Si534 uses one fixed crystal to
provide a wide range of output frequencies. This IC-based approach allows
the crystal resonator to provide exceptional frequency stability and reliability.
In addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low jitter clocks in noisy environments
typically found in communication systems. The Si534 IC-based XO is factory
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, and temperature stability. Specific
configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
Functional Block Diagram
VDD CLK– CLK+
Pin Assignments:
See page 6.
(Top View)
NC 1
FS[1]
7
6
VDD
OE 2
5 CLK–
GND 3
4 CLK+
8
FS[0]
(LVDS/LVPECL/CML)
NC 1
FS[1]
7
6
VDD
OE 2
5 NC
FS[1]
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL®
Clock
Synthesis
FS[0]
GND 3
4
8
FS[0]
(CMOS)
CLK
Rev. 1.4 6/18
OE GND
Copyright © 2018 by Silicon Laboratories
Si534



Si534
Si534
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition Min Typ Max Units
Supply Voltage1
VDD 3.3 V option
2.5 V option
2.97 3.3 3.63 V
2.25 2.5 2.75 V
1.8 V option
1.71 1.8 1.89 V
Supply Current
IDD Output enabled
LVPECL
— 111 121
CML
— 99 108 mA
LVDS
90 98
CMOS
81 88
Tristate mode — 60 75 mA
Output Enable (OE)
and Frequency Select FS[1:0]2
VIH
0.75 x VDD
—V
VIL — — 0.5 V
Operating Temperature Range
TA
–40 — 85 ºC
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE and FS[1:0] pins include a 17 kpullup resistor to VDD.
Table 2. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min Typ Max Units
Nominal Frequency1,2
fO LVPECL/LVDS/CML 10 — 945 MHz
CMOS
10 — 160 MHz
Initial Accuracy
Temperature Stability1,3
fi
Measured at +25 °C at time of
shipping
±1.5
— ppm
–7 — +7
–20 — +20 ppm
–50 — +50
Aging
Frequency drift over first year
fa Frequency drift over 20-year life —
— ±3 ppm
— ±10 ppm
Total Stability
Temp stability = ±7 ppm
— — ±20 ppm
Temp stability = ±20 ppm — — ±31.5 ppm
Temp stability = ±50 ppm — — ±61.5 ppm
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
2 Rev. 1.4





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