CLOCK GENERATOR. Si52131-A11A Datasheet

Si52131-A11A GENERATOR. Datasheet pdf. Equivalent

Part Si52131-A11A
Description CLOCK GENERATOR
Feature Si52131-A11A PCI-EXPRESS GEN1, GEN2, & GEN3 TWO OUTPUT CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK .
Manufacture Silicon Laboratories
Datasheet
Download Si52131-A11A Datasheet



Si52131-A11A
Si52131-A11A
PCI-EXPRESS GEN1, GEN2, & GEN3 TWO OUTPUT CLOCK GENER-
ATOR WITH 25 MHZ REFERENCE CLOCK & ACTIVE LOW OE PINS
Features
PCI-Express Gen1, Gen2 &
Gen3 Compliant
25 MHz Crystal Input or Clock
input
Supports Serial ATA (SATA) at I2C support with readback
100 MHz
capabilities
Low power differential output
buffers
Triangular spread spectrum
profile for maximum
No termination resistors required electromagnetic interference
Dedicated active low output
(EMI) reduction
enable pins for each output
Extended Temperature
Pin selectable spread control
–40 to 85oC
Selectable frequencies: 100, 125, 3.3 V Power supply
and 200 MHz
24-pin QFN package
Up two PCI-Express clocks
25 MHz reference clock
Ordering Information:
See page 17
Pin Assignments
Applications
Network Attached Storage
Wireless Access Point
Multi-function Printer
Routers
Ideal for Thunderbolt applications
Description
Si52131-A11A is a high-performance, PCIe clock generator that can
source two PCIe clocks and a buffered 25 MHz reference clock from a
25 MHz crystal or clock input. The PCIe clock outputs are compliant to
PCIe Gen 1, Gen 2, and Gen 3 specifications. The device has three
active low output enable pins for enabling and disabling each output. The
device features two input select pins for frequency selection and spread
control. The small footprint and low power consumption makes Si52131-
A11A the ideal clock solution for consumer and embedded applications.
VDD_REF 1
REF 2
OE_REF1 3
VSS_REF 4
OE_DIFF01 5
VDD_DIFF 6
24 23 22 21 20 19
18 OE_DIFF11
17 VDD_DIFF
25
GND
16 DIFF1
15 DIFF1
14 DIFF0
13 DIFF0
7 8 9 10 11 12
Note
1. Internal 100 k-ohm pull-down resistor
Patents pending
Functional Block Diagram
XIN/CLKIN
XOUT
SCLK
SDATA
OE#_REF
OE#_DIFF [1:0]
SSC [1:0]
PLL1
(SSC)
Control & Memory
Control RAM
Divider
25MHz
DIFF0
DIFF1
Rev 1.0 3/13
Copyright © 2013 by Silicon Laboratories
Si52131-A11A



Si52131-A11A
Si52131-A11A
2 Rev 1.0





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