Clock Generator. Si52208 Datasheet

Si52208 Generator. Datasheet pdf. Equivalent

Part Si52208
Description 12/8/4/2-Output PCI-Express Gen 1/2/3/4/5 and SRIS Clock Generator
Feature Si52212/Si52208/Si52204/Si52202 Data Sheet 12/8/4/2-Output PCI-Express Gen 1/2/3/4/5 and SRIS Clock.
Manufacture Silicon Laboratories
Datasheet
Download Si52208 Datasheet



Si52208
Si52212/Si52208/Si52204/Si52202
Data Sheet
12/8/4/2-Output PCI-Express Gen 1/2/3/4/5 and SRIS Clock
Generator
The Si52212/08/04/02 are the industry's highest performance and lowest power PCI Ex-
press clock generator family for 1.5–1.8 V PCIe Gen 1/2/3/4/5 and SRIS applications.
The Si52212, Si52208, and Si52204 can source twelve, eight, and four 100 MHz PCIe
differential clock outputs, respectively, plus one 25 MHz LVCMOS reference clock out-
put. The Si52202 can source two 100 MHz PCIe clock outputs only. All differential clock
outputs are compliant to PCIe Gen1/2/3/4/5 common clock and separate reference clock
architectures specifications.
The Si52212/08/04/02 feature individual hardware control pins for enabling and disa-
bling each output, spread spectrum enable/disable for EMI reduction, and frequency se-
lect to select 100, 133, or 200 MHz differential output frequencies. These features can
also be controlled via I2C.
The small footprint and low power consumption make this family of PCIe clock genera-
tors ideal for industrial and consumer applications.
For more information about PCI-Express, Silicon Labs' complete PCIe portfolio, applica-
tion notes, and design tools, including the Silicon Labs PCIe Clock Jitter Tool for PCI-
Express compliance, please visit the Silicon Labs PCI Express Learning Center.
Applications
• Servers
• Storage
• Data Centers
• PCIe Add-on Cards
• Network Interface Cards (NIC)
• Graphics Adapter Cards
• Multi-function Printers
• Digital Single-Lens Reflex (DSLR) Cameras
• Digital Still Cameras
• Digital Video Cameras
• Docking Stations
KEY FEATURES
• 12/8/4/2-output low-power, push-pull HCSL
compatible PCI-Express Gen 1, Gen 2,
Gen 3, Gen 4, Gen 5, and SRIS-compliant
outputs
• Low jitter: 0.13 ps rms max, Gen 5
Individual hardware control pins and I2C
controls for Output Enable, Spread
Spectrum Enable and Frequency Select
• Triangular spread spectrum for EMI
reduction, down spread 0.25% or 0.5%
• Internal 100 Ω or 85 Ω line matching
• Adjustable output slew rate
• Power down (PWRDNb) function supports
Wake-on LAN (except Si52202)
• One non-spread, LVMCOS reference clock
output (except Si52202)
• Frequency Select to select 133 MHz or
200 MHz (except Si52202)
• 25 MHz crystal input or clock input
I2C support with readback capabilities
• Extended temperature: –40 to 85 °C
• 1.5–1.8 V power supply, with separate
VDD and VDD_IO
• Small QFN packages
• Pb-free, RoHS-6 compliant
silabs.com | Building a more connected world.
Rev. 1.0



Si52208
1. Feature List
Data Sheet
Feature List
• 12/8/4/2-output 100 MHz PCIe Gen 1/2/3/4/5 and SRIS compliant clock generator, with push-pull HCSL output drivers
• High port count with push-pull HCSL outputs to support highly integrated solution, eliminating external resistors for the HCSL out-
put drivers
• Low jitter of 0.13 ps rms max to meet PCIe Gen5 specifications with design margin
• Low power consumption.
• Lowest power consumption in the industry for a 2-output PCIe clock generator
Individual hardware control pins and I2C controls for Output Enable, Spread Spectrum Enable and Frequency Select
• Output Enable function easily disables unused outputs for power saving
• Spread Enable function to turn on/off spread spectrum and to select spread levels, either down spread 0.25% or 0.5%
• Frequency Select function to select output frequency of 100 MHz, 133 MHz, or 200 MHz (except Si52202 where the output fre-
quency is limited to 100 MHz. Please contact Silicon Labs for 133 MHz or 200 MHz in Si52202)
All above functions are controlled by individual hardware pins or I2C
• Internal 100 Ω or 85 Ω impedance matching
• Eliminates external line matching resistor to reduce board space
• Adjustable slew rate to improve signal quality for different applications and board designs
• Power down (PWRDNb) function supports Wake-on LAN (except Si52202)
• One non-spread, 25 MHz LVMCOS reference clock output (except Si52202)
• A buffered 25 MHz LVCMOS clock output to drive ASICS or SoCs on board
• 25 MHz reference input
• Supports a standard crystal or clock input for flexibility
I2C support with readback capabilities
• 1.5–1.8 V power supply with separate VDD and VDD_IO (1.05 to 1.8 V)
• Temperature range: –40 °C to 85 °C
• Small QFN packages to optimize board space. Smallest 2-output PCIe clock generator in the industry
• 64-pin QFN (9 x 9 mm) : 12-output
• 48-pin QFN (6 x 6 mm) : 8-output
• 32-pin QFN (5 x 5 mm) : 4-output
• 20-pin QFN (3 x 3 mm) : 2-output
• Pb-free, RoHS-6 compliant
silabs.com | Building a more connected world.
Rev. 1.0 | 2





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