Clocks Supporting. Si5384 Datasheet

Si5384 Supporting. Datasheet pdf. Equivalent

Part Si5384
Description Network Synchronizer Clocks Supporting
Feature Si5383/84 Rev D Data Sheet Network Synchronizer Clocks Supporting 1 PPS to 750 MHz Inputs The Si538.
Manufacture Silicon Laboratories
Datasheet
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Si5384
Si5383/84 Rev D Data Sheet
Network Synchronizer Clocks Supporting 1 PPS to 750 MHz
Inputs
The Si5383/84 combines the industry’s smallest footprint and lowest power network syn-
chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The
Si5383/84 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless
communications systems, and data center switches requiring both traditional and packet
based network synchronization.
The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE 1588
DCO, or a general-purpose PLL for processor/FPGA clocking. The Si5383/84 can also
be used in legacy SETS systems needing Stratum 3/3E compliance. In addition, locking
to a 1 PPS input frequency is available on DSPLL D. The DCO mode provides precise
timing adjustment to 1 part per trillion (ppt). The unique design of the Si5383/84 allows
the device to accept a TCXO/OCXO reference with a wide frequency range, and the ref-
erence clock jitter does not degrade the output performance. The Si5383/84 is configura-
ble via a serial interface and programming the Si5383/84 is easy with ClockBuilder Pro
software. Factory pre-programmed devices are also available.
Applications
• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
• Telecom Grand Master Clock (T-GM) as defined by ITU-T G.8273.1
• Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined by ITU-T G.
8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813, GR-1244, GR-253 network synchronization
• 1 Hz/1 PPS Clock Multiplier
KEY FEATURES
• One or three independent DSPLLs in a
single monolithic IC supporting flexible
SyncE/IEEE 1588 and SETS architectures
• Input frequency range:
• External crystal: 25-54 MHz
• REF clock: 5-250 MHz
• Diff clock: 8 kHz - 750 MHz
• LVCMOS clock: 1 PPS, 8 kHz - 250
MHz
• Output frequency range:
• Differential: 1 PPS, 100 Hz - 718.5 MHz
• LVCMOS: 1 PPS, 100 Hz - 250 MHz
• Ultra-low jitter of less than 150 fs
Si5383/84
IN4
IN3
XTAL
OCXO/
TCXO
XB XA REFb REF
OSC
DSPLL
D
IN2 ÷FRAC
IN1 ÷FRAC
IN0 ÷FRAC
I2C
Control/
Status
DSPLL A
DSPLL C
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
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Si5384
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 DSPLL Loop Bandwidth in Standard Input Mode . . . . . . . . . . . . . . . . . . 4
3.3.1 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.4 DSPLL Loop Bandwidth in 1 PPS Mode . . . . . . . . . . . . . . . . . . . . . 4
3.4.1 Smartlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5.1 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5.2 Free-run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5.3 Lock Acquisition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5.4 Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5.5 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.6 Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . 7
3.6.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC) . . . . . . . . . . . 7
3.6.2 Frequency Increment/Decrement Using the Serial Interface . . . . . . . . . . . . . . 8
3.7 External Reference (XA/XB, REF/REFb) . . . . . . . . . . . . . . . . . . . . . 8
3.7.1 External Crystal (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.7.2 External Reference (REF/REFb) . . . . . . . . . . . . . . . . . . . . . . .10
3.8 Inputs (IN0, IN1, IN2, IN3, IN4) . . . . . . . . . . . . . . . . . . . . . . . .11
3.8.1 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.8.2 Manual Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.8.3 Automatic Input Selection in Standard Input Mode . . . . . . . . . . . . . . . . .11
3.8.4 Input Configuration and Terminations . . . . . . . . . . . . . . . . . . . . .12
3.8.5 Hitless Input Switching in Standard Input Mode . . . . . . . . . . . . . . . . . .13
3.8.6 Ramped Input Switching in Standard Input Mode . . . . . . . . . . . . . . . . .13
3.8.7 Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . .13
3.8.8 Synchronizing to Gapped Input Clocks in Standard Input Mode . . . . . . . . . . . .13
3.9 Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.9.1 Input LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.9.2 XA/XB LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.9.3 OOF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.9.4 Precision OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.9.5 Fast OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.9.6 LOL Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.9.6.1 LOL Detection Standard Input Mode . . . . . . . . . . . . . . . . . . . . .17
3.9.6.2 LOL Detection in 1 PPS Mode . . . . . . . . . . . . . . . . . . . . . . .17
3.9.7 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.10 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
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