CRYSTAL OSCILLATOR. Si550 Datasheet

Si550 OSCILLATOR. Datasheet pdf. Equivalent

Part Si550
Description VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR
Feature Si550 REVISION D VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ Features  Availab.
Manufacture Silicon Laboratories
Datasheet
Download Si550 Datasheet



Si550
Si550
REVISION D
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)
10 MHZ TO 1.4 GHZ
Features
Available with any frequency from Internal fixed crystal frequency
10 to 945 MHz and select
ensures high reliability and low
frequencies to 1.4 GHz
aging
3rd generation DSPLL® with
Available CMOS, LVPECL,
superior jitter performance (0.5 ps) LVDS, and CML outputs
3x better temperature stability than 3.3, 2.5, and 1.8 V supply options
SAW-based oscillators
Industry-standard 5 x 7 mm
Excellent PSRR performance
package and pinout
Pb-free/RoHS-compliant
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to
provide a low-jitter clock at high frequencies. The Si550 supports any
frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike
traditional VCXOs, where a different crystal is required for each output
frequency, the Si550 uses one fixed crystal to provide a wide range of output
frequencies. This IC-based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low-jitter clocks in noisy environments typically found in
communication systems. The Si550 IC-based VCXO is factory-configurable
for a wide variety of user specifications, including frequency, supply voltage,
output format, tuning slope, and temperature stability. Specific configurations
are factory programmed at time of shipment, thereby eliminating the long
lead times associated with custom oscillators.
Functional Block Diagram
VDD
Si5602
Ordering Information:
See page 10.
Pin Assignments:
See page 9.
(Top View)
VC 1
OE 2
GND 3
6 VDD
5 CLK–
4 CLK+
Fixed
Frequency
XO
Any-Frequency
10 MHz–1.4 GHz
DSPLL®
Clock Synthesis
CLK+
CLK–
Vc ADC
OE
Rev. 1.2 6/18
GND
Copyright © 2018 by Silicon Laboratories
Si550



Si550
Si550
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition Min Typ Max
Supply Voltage1
VDD 3.3 V option
2.5 V option
2.97 3.3 3.63
2.25 2.5 2.75
1.8 V option
1.71 1.8 1.89
Supply Current
IDD Output enabled
LVPECL
— 120 130
CML
— 108 117
LVDS
99 108
CMOS
90 98
tristate mode
— 60 75
Output Enable (OE)2
VIH
0.75 x VDD
VIL — — 0.5
Operating Temperature Range
TA
–40 — 85
Notes:
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 10 for further details.
2. OE pin includes a 17 kresistor to VDD.
Units
V
V
V
mA
mA
V
V
°C
Table 2. VC Control Voltage Input
Parameter
Symbol Test Condition
Min
Typ
Max Units
Control Voltage Tuning Slope1,2,3
KV
10 to 90% of VDD
33
— 45 —
90
135
ppm/V
— 180 —
— 356 —
Control Voltage Linearity4
LVC
BSL
–5 ±1 +5 %
Incremental
–10 ±5 +10 %
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
VC Input Impedance
ZVC
500 —
— k
Nominal Control Voltage
VCNOM
@ fO
— VDD/2 —
V
Control Voltage Tuning Range
VC
0
VDD
V
Notes:
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 10.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
2 Rev. 1.2





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